Schedulability analysis for global fixed-priority scheduling of the 3-phase task model

Abstract

Scheduling real-time applications on general purpose multicore platforms is a challenging problem from atiming analysis perspective. Such platforms expose uncontrolledsources of interference whenever concurrent accesses to memoryare performed. The non-deterministic bus and memory accessbehavior complicates the estimations of applications 19 worst-caseexecution times (WCET).The 3-phase task model seems a good candidate to circumventthe uncontrolled sources of interference by isolating concurrentmemory accesses. A task is divided in three successive phases;first, the task loads its instruction and data in a local memory,then it executes nonpreemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back tomain memory. Following this execution model, tasks never accessthe bus during their execution phase. Instead, all the bus accessesare performed during the first and third phases.In this paper, we focus on the global fixed-priority schedulingof the 3-phase task model. A new schedulability test is derivedby modelling the interference happening on the bus rather thanthe interference on the cores as in the state-ot-the-art techniques.The effectiveness of the test is evaluated by comparing it againstthe state-of-the-art. Abstract-Scheduling real-time applications on general purpose multicore platforms is a challenging problem from a timing analysis perspective. Such platforms expose uncontrolled sources of interference whenever concurrent accesses to memory are performed. The non-deterministic bus and memory access behavior complicates the estimations of applications' worst-case execution times (WCET).The 3-phase task model seems a good candidate to circumvent the uncontrolled sources of interference by isolating concurrent memory accesses. A task is divided in three successive phases; first, the task loads its instruction and data in a local memory, then it executes non-preemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back to main memory. Following this execution model, tasks never access the bus during their execution phase. Instead, all the bus accesses are performed during the first and third phases.In this paper, we focus on the global fixed-priority scheduling of the 3-phase task model. A new schedulability test is derived by modelling the interference happening on the bus rather than the interference on the cores as in the state-ot-the-art techniques. The effectiveness of the test is evaluated by comparing it against the state-of-the-art.

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

“…Maia et al [43] performed a schedulability test focused on the global fixed-priority scheduling of the 3-phase task model by modelling interference on the shared bus. The 3phase task model divides tasks into three successive phases: Acquisition, Execution, and Restitution.…”

“…The study does not require information about the resource demands of tasks on other cores. The schedulability analysis proposed by Maia et al [43] is performed from the perspective of the bus. The interference is modelled considering the total demand of the resource in a time window.…”

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

“…In addition, AER [9,29,30] allows the parallel execution of tasks in each core to improve the limitations of TDMA, as shown in Figure 4b. Tasks are divided into three phases: acquisition, execution, and restitution (denoted by A, E, and R, respectively).…”

“…However, the user API (system call) and kernel API needed to be modified for the PEW model. Similar to the PEW model, there are studies on the AER models [9,29,30]. The AER model, similar to other models, executes the A and R phases that access memory in parallel with the E phase.…”

Code generation for multi-phase tasks on a multi-core distributed memory platform

“…Finally, the Restitution phase copies the results of the E-phase back into the main memory, for use by other tasks. This simplifies timing analysis because: 1) communication phases are clearly identified, so the system scheduler can schedule communications [1,14] and avoid contentions; 2) worst-case execution time analysis (WCET) of computation phases does not need to take bus contentions into account [23].…”