Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

Abstract

Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

“…A pseudo-partition ensures that accesses to the shared resources of each partition do not interfere with each other. Subsequently, Park et al [39] proposed a multi-TDMA model. The proposed model allows the simultaneous execution of two cores, taking into account that the memory bus of the target board can process two requests simultaneously.…”

“…Compared to the TDMA model, running the AER model uses fewer memory areas. Later, Park et al [39] proposed a multi-TDMA model. The evaluation shows that the multi-TDMA model has higher utilization than the TDMA model and a lower execution time than the AER model.…”

“…Table 6 shows a summary of the main approaches to reduce interference on the shared memory bus. [157] Bandwidth Regulator Memory bandwidth allocation Software HRT/SRT [158] Bandwidth Regulator Prioritize soft real-time applications Software SRT [32] Bandwidth Regulator Focuses on partitioned scheduling Software SRT [160] Bandwidth Regulator Budget-based memory bandwidth regulation Software SRT [159] Bandwidth Regulator Dynamic memory bandwidth allocation None HRT [33], [161] Bandwidth Regulator Re-design of memory controllers Hardware HRT/SRT [34] Bandwidth Regulator New memory controller architecture Hardware SRT [35] Bandwidth Regulator Memory Inter-Arrival Time Traffic Shaping Hardware SRT [36] Bandwidth Regulator Bandwidth Regulation Unit (BRU) Hardware SRT [168] Offline Scheduling Execution model composed of rules Soft/Hard HRT [167] Offline Scheduling Scheduling table Software HRT [37], [163] Phased Execution Model Predictable Execution Model Software SRT [165] Phased Execution Model Acquisition Execution Restitution Software HRT [166] Phased Execution Model Execution profile and resource allocation Hard/Soft SRT [170] Hardware isolation Arbitration policy Hardware SRT [38], [171] Hardware isolation TDMA arbitration policy Hardware HRT [173], [174] Hardware isolation Time Division Multiplexing (TDM) Hardware SRT [39] Hardware isolation Multi-TDMA model Hardware HRT [31] Bandwidth Regulator Memory bandwidth reservation mechanism Software AVG [40] Other Approaches Persistence-aware bus contention analysis None AVG [41] Other Approaches Bounding the worst-case bus contention Hardware AVG…”

Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration scheme

“…This ensures that tasks can issue memory requests only during their memory phase(s), which facilitates the analysis of the bus contention that can be suffered by tasks. Under the umbrella of phased-execution models, the 3-phase execution model has received much attention from industry and academia [14,15,8,16,10,17,18,19,12,20,21,22,23]. In the 3-phase task execution model, the execution of a task is divided into three phases Acquisition (A-phase), Execution (E-phase), and Restitution (R-phase).…”