Code generation for multi-phase tasks on a multi-core distributed memory platform

Fort, Frédéric; Forget, Julien

doi:10.1109/rtcsa.2019.8864558

Cited by 3 publications

(3 citation statements)

References 32 publications

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“…The tasks explicitly trigger memory copies between main and scratchpad memories before starting the computation. In many cases, this separation of code between memory phase and computation phase can be performed automatically, for example when compiling code from high-level programming languages like Prelude [9], or by modifying existing compilers [22]. We assume that the separation between the two phases has been done either manually by the programmer, or by an appropriate code generation tool.…”

Section: System Model a Architecture Modelmentioning

confidence: 99%

Contention-free scheduling of PREM tasks on partitioned multicore platforms

Senoussaoui

Zahaf

Lipari

et al. 2022

2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA)

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Commercial-off-the-shelf (COTS) platforms feature several cores that share and contend for memory resources. In real-time system applications, it is of paramount importance to correctly estimate tight upper bounds to the delays due to memory contention. However, without proper support from the hardware (e.g. a real-time bus scheduler), it is difficult to estimate such upper bounds.This work aims at avoiding contention for a set of tasks modeled using the Predictable Execution Model (PREM), i.e. each task execution is divided into a memory phase and a computation phase, on a hardware multicore architecture where each core has its private scratchpad memory and all cores share the main memory. We consider non-preemptive scheduling for memory phases, whereas computation phases are scheduled using partitioned preemptive EDF. In this work, we propose three novel approaches to avoid contention in memory phases: (i) a task-level time-triggered approach, (ii) job-level time-triggered approach, and (iii) on-line scheduling approach. We compare the proposed approaches against the state of the art using a set of synthetic experiments in terms of schedulability and analysis time. Furthermore, we implemented the different approaches on an Infineon AURIX TC397 multicore microcontroller and validated the proposed approaches using a set of tasks extracted from well-known benchmarks from the literature.

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Section: System Model a Architecture Modelmentioning

confidence: 99%

Contention-free scheduling of PREM tasks on partitioned multicore platforms

Senoussaoui

Zahaf

Lipari

et al. 2022

2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA)

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“…One problem with the multi-phase model is that developers must manually port the existing code as a multi-phase task. To solve this problem, tools have been studied for analyzing code and converting it for multi-phase models [42,43]. In particular, there is a study that proposes a C-language-based tool to eliminate compiler dependence in code generation [42].…”

Section: Related Workmentioning

confidence: 99%

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

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“…This ensures that tasks can issue memory requests only during their memory phase(s), which facilitates the analysis of the bus contention that can be suffered by tasks. Under the umbrella of phased-execution models, the 3-phase execution model has received much attention from industry and academia [14,15,8,16,10,17,18,19,12,20,21,22,23]. In the 3-phase task execution model, the execution of a task is divided into three phases Acquisition (A-phase), Execution (E-phase), and Restitution (R-phase).…”

Section: Introductionmentioning

confidence: 99%