Scaling to 50-nm C-axis aligned crystalline In-Ga-Zn oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory

Kobayashi, Y.; Matsubayashi, Daisuke; Nagatsuka, Shuhei; Yakubo, Yuto; Atsumi, Tomoaki; Shionoiri, Yutaka; Hondo, Suguru; Yamamoto, T.; Okazaki, Yutaka; Nagai, Masako; Sasagawa, Shinya; Ito, Daisuke; Hata, Yuki; Hamada, Takashi; Arasawa, Ryo; Hanaoka, Kazuya; Sakakura, Masaaki; Suzawa, Hideomi; Yamamoto, Yoshitaka; Yamazaki, Shunpei

doi:10.1109/vlsit.2014.6894421

Cited by 21 publications

(13 citation statements)

References 3 publications

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“…Our previous studies revealed that S-ch CAAC-IGZO FETs show very high resistance to short channel effects. 14) The active layer of S-ch CAAC-IGZO FETs was formed by DC sputtering to a thickness of 40 nm under the same conditions as those for the planar CAAC-IGZO FETs. The CAAC-IGZO film was etched to form an island whose width was 0.047 µm, and the source and drain electrodes were formed.…”

Section: Experimental Methodsmentioning

confidence: 99%

Channel length dependence of field-effect mobility ofc-axis-aligned crystalline In–Ga–Zn–O field-effect transistors

Matsuda¹,

Kikuchi²,

Yamane³

et al. 2015

Jpn. J. Appl. Phys.

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Field-effect transistors (FETs) with c-axis-aligned crystalline In-Ga-Zn-O (CAAC-IGZO) active layers have extremely low off-state leakage current. Exploiting this feature, we investigated the application of CAAC-IGZO FETs to LSI memories. A high on-state current is required for the high-speed operation of these LSI memories. The field-effect mobility μ FE of a CAAC-IGZO FET is relatively low compared with the electron mobility of singlecrystal Si (sc-Si). In this study, we measured and calculated the channel length L dependence of μ FE for CAAC-IGZO and sc-Si FETs. For CAAC-IGZO FETs, μ FE remains almost constant, particularly when L is longer than 0.3 µm, whereas that of sc-Si FETs decreases markedly as L shortens. Thus, the μ FE difference between both FET types is reduced by miniaturization. This difference in μ FE behavior is attributed to the different susceptibilities of electrons to phonon scattering. On the basis of this result and the extremely low off-state leakage current of CAAC-IGZO FETs, we expect high-speed LSI memories with low power consumption.

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Section: Experimental Methodsmentioning

confidence: 99%

Channel length dependence of field-effect mobility ofc-axis-aligned crystalline In–Ga–Zn–O field-effect transistors

Matsuda¹,

Kikuchi²,

Yamane³

et al. 2015

Jpn. J. Appl. Phys.

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show abstract

“…Off-state current is as low as 6 yA/ lm at 85 C. As the channel length becomes shorter, on-state current becomes higher and 13 This indicates that the CAAC-IGZO transistor can achieve highly efficient nonvolatile memory. Improved characteristics from scaling will result in shorter backup time.…”

Section: Potential Performance Of Caac-igzo Transistormentioning

confidence: 99%

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor

et al. 2014

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“…With regard to scaling, transistor characteristics of a CAAC-IGZO FET with a channel length of 50 nm [38] and retention characteristics of memory with a hybrid process that involves a 0.18 m CMOS FET and 0.35 m CAAC-IGZO FET [39] have been reported, and no large increase in off-state current due to scaling is expected. It is our challenge to scale down the technology and to evaluate the effectiveness of Noff computing on low-voltage operation due to scaling.…”

Section: A Process Technologymentioning

confidence: 99%

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Aoki

Okamoto

Nakagawa

et al. 2015

IEEE J. Solid-State Circuits

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Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 µm crystalline oxide semiconductor FET on a 0.5 µm CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.Index Terms-CAAC-IGZO, crystalline IGZO, crystalline oxide semiconductor, field programmable gate array, multicontext, nonvolatile memory, normally-off computing, oxide semiconductor, power gating, shadow register. 0018-9200

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Scaling to 50-nm C-axis aligned crystalline In-Ga-Zn oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory

Cited by 21 publications

References 3 publications

Channel length dependence of field-effect mobility ofc-axis-aligned crystalline In–Ga–Zn–O field-effect transistors

Channel length dependence of field-effect mobility ofc-axis-aligned crystalline In–Ga–Zn–O field-effect transistors

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

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