Scaling of Nanocrystal Memory Cell by Direct Tungsten Bitline on Self-Aligned Landing Plug Polysilicon Contact

Kim, Ilgweon; Yanagidaira, Kosuke; Hiramoto, Toshiro

doi:10.1109/led.2004.826542

Cited by 13 publications

(12 citation statements)

References 12 publications

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“…Physical separation of nanocrystals can improve the retention time by limiting the lateral flow of charges. The new function that appears in a silicon nanocrystal memory cell is the two-bit-per-cell operation [21]. The electrons are locally injected only near drain and/or source by hot-carrier injection, and there are four states depending on where the electrons are injected.…”

Section: Memorymentioning

confidence: 99%

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Emerging nanoscale silicon devices taking advantage of nanostructure physics

2006

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This paper describes the present status of research on emerging nanoscale silicon devices that take full advantage of new physical phenomena which appear in silicon nanostructures. This new physics includes quantum effects that enhance the performance of MOS transistors and single-electron charging effects that add new function to conventional CMOS circuits. These physical phenomena may be used to extend the scaling and performance limits of conventional CMOS.

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Section: Memorymentioning

confidence: 99%

“…The electrons are locally injected only near drain and/or source by hot-carrier injection, and there are four states depending on where the electrons are injected. Distinct four-threshold voltages are experimentally observed that can be read out [21].…”

Section: Memorymentioning

confidence: 99%

Emerging nanoscale silicon devices taking advantage of nanostructure physics

2006

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“…The manufacturing process for fabricating phosphorus (P)-doped polysilicon and silicon (Si) selective epitaxial growth plugs continues to receive more attention as a key factor for high-performance semiconductor devices. [1][2][3][4][5][6][7][8][9] A variety of physical phenomena, such as P diffusion by subsequent heat treatment, interfacial defect segregation, and the creation and destruction of crystal defects, is expected to occur within a poly-Si plug structure. Therefore, high-quality poly-Si contacts are formed that should be observed closely to increase the understanding of these phenomena.…”

Section: Introductionmentioning

confidence: 99%

Annihilation Behavior of Planar Defects on Phosphorus-Doped Silicon at Low Temperatures

D.-H.¹,

Kim²,

Jeong³

et al. 2017

j nanosci nanotechnol

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The planar defect behavior and phosphorus (P) diffusion of P-doped silicon (Si) thin film on monocrystalline Si with annealing was investigated by high-resolution transmission electron microscopy. These images indicate that the as-deposited Si thin film crystallizes with many planar defects, such as stacking faults and twin boundaries. Secondary ion mass spectroscopy and atom probe tomography reveal that P atoms are segregated to the planar defects and diffuse out the Si substrate at 600 C. The solubility of P atoms has an influence on the rearrangement of Si atoms, which leads to the annihilation of the defects in the deposited Si thin film.

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“…The silicon nanocrystal memory [1][2][3][4][5][6][7][8][9][10][11] is an attractive candidate for future flash memory cell structure. One of the serious problems associated with this memory for practical use is its small threshold voltage shift (ÁV th ) particularly when multibit operation is required for mass storage applications.…”

Section: Introductionmentioning

confidence: 99%

Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin-Body Silicon Nanocrystal Memories

Yanagidaira

Saitoh²,

Hiramoto³

2005

Jpn. J. Appl. Phys.

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High performance Schottky diodes formed with a BCl 3 passivation layer on Pt/Al/n-InP are presented. The diode realizes a barrier height as high as 0.85 eV, and the reverse current density is 1:44 Â 10 À6 A/cm 2 at À3 V. Secondary ion mass spectroscopy for depth profiles measurements reveals the existence of B and Cl elements at the contact interface. The electron spectroscopy chemical analysis shows that the surface layer of the passivated InP substrate is composed of InPO 4 and chloride. The improvement of the barrier height of Pt/Al/n-InP diode is presumably due to the formation of the aluminum oxide at the contact interface and due to the chlorine passivation on the interface states.

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Scaling of Nanocrystal Memory Cell by Direct Tungsten Bitline on Self-Aligned Landing Plug Polysilicon Contact

Cited by 13 publications

References 12 publications

Emerging nanoscale silicon devices taking advantage of nanostructure physics

Emerging nanoscale silicon devices taking advantage of nanostructure physics

Annihilation Behavior of Planar Defects on Phosphorus-Doped Silicon at Low Temperatures

Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin-Body Silicon Nanocrystal Memories

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