Scaling effects on microstructure and electromigration reliability for Cu and Cu(Mn) interconnects

Cao, Linjun; Zhang, Lijuan; Ho, Paul S.; Justison, Patrick; Hauschildt, M.

doi:10.1109/irps.2014.6860660

Cited by 14 publications

(10 citation statements)

References 10 publications

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“…The remaining 30% grains had other orientations. Whereas, (Cao et al 2013;Cao et al 2014) have observed a preferred orientation of (110) along the trench normal and (111) along the trench width in 70 nm patterned copper lines. This difference in preferred orientation could possibly be due to different processing conditions.…”

Section: Grain Oreintation Assignmentmentioning

confidence: 97%

“…4), Sentaurus Structure Editor. A bamboo polycrystalline structure is observed in metal lines with a lognormal grain size distribution (Cao et al 2014;Rizzolo 2014;Meyer et al 2005. A typical observance that grains are smaller at the bottom and larger at the top of the trench as been made from experiments (Cao et al 2013;Karmarkar et al 2012;B.…”

Section: Test Structuresmentioning

confidence: 99%

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Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Basavalingappa

Shen

Lloyd

2017

Mech Adv Mater Mod Process

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Background: Copper is the primary metal used in integrated circuit manufacturing of today. Even though copper is face centered cubic it has significant mechanical anisotropy depending on the crystallographic orientations. Copper metal lines in integrated circuits are polycrystalline and typically have lognormal grain size distribution. The polycrystalline microstructure is known to impact the reliability and must be considered in modeling for better understanding of the failure mechanisms. Methods: In this work, we used Voronoi tessellation to model the polycrystalline microstructure with lognormal grainsize distribution for the copper metal lines in test structures. Each of the grains is then assigned an orientation with distinct probabilistic texture and corresponding anisotropic elastic constants based on the assigned orientation. The test structure is then subjected to a thermal stress.

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Section: Grain Oreintation Assignmentmentioning

confidence: 97%

Section: Test Structuresmentioning

confidence: 99%

Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Basavalingappa

Shen

Lloyd

2017

Mech Adv Mater Mod Process

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“…It can also be seen from the table that Mn acts an alloy element even better than Al (5% resistance increase with EM t50 ratio 10 times enhancement). In fact, it has been recently reported that Mn may serve a good alloy element for future technology node [9]. Fig.…”

Section: Resultsmentioning

confidence: 99%

Effect of alloy seed on Cu interconnect electromigration and stress migration

Zhao

Chang

2014

Microelectronic Engineering

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“…However, scaling can significantly reduce the electromigration (EM) lifetime for Cu interconnects, raising serious reliability concern for advanced technology nodes. Some improvements have been developed to improve EM and to extend the technology node by using CoWP metal cap [247,248] and Mn alloying [249][250][251].…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

“…A self-forming barrier uses a Cu-X alloy-based seed layer to form the barrier layer by post metallization annealing. Among the tested alloying elements are V, Al, and Mn [249][250][251]271,272]. Mn-based self-formed barrier (SFB) is an attractive alternative technique from RC performance point of view.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Scaling effects on microstructure and electromigration reliability for Cu and Cu(Mn) interconnects

Cited by 14 publications

References 10 publications

Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Effect of alloy seed on Cu interconnect electromigration and stress migration

State of the Art and Future Perspectives in Advanced CMOS Technology

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