Scalable parallel simulation of networks on chip

Eggenberger, Marcus; Radetzki, Marian

doi:10.1109/nocs.2013.6558402

Cited by 11 publications

(5 citation statements)

References 15 publications

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“…However, this approach requires simulation kernel modifications, which our approach does not require. In another approach [15], simulation parallelisation has been explored to take advantage of multiple CPU cores on the host simulation machine. By effectively dividing the independent tasks, a speedup almost linearly proportional to the number of cores can be demonstrated.…”

Section: Literature Reviewmentioning

confidence: 99%

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Harbin

Indrusiak

2016

Journal of Systems Architecture

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Article:Harbin, James orcid.org/0000-0002-6479-8600 and Soares Indrusiak, Leandro orcid.org/0000-0002- 9938-2920 (2016) AbstractThe simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of stateof-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput and latency performance of the system. This paper presents a series of network-on-chip transaction-level model (TLM) algorithms that provide a highly abstracted view of the process of data transmission in priority preemptive and non-preemptive networks-on-chip, which permit a major reduction in simulation event count. These simulation models are tested using two realistic application case studies and with synthetic traffic. Results presented demonstrate that these lightweight TLM simula- * Corresponding author: Telephone +44 (0) tion models can produce latency figures accurate to within mere flits for the majority of flows, and more than 93% accurate link dynamic power consumption modelling, while simulating 2.5 to 3 orders of magnitude faster when compared to a cycle-accurate model of the same interconnect.

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Section: Literature Reviewmentioning

confidence: 99%

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Harbin

Indrusiak

2016

Journal of Systems Architecture

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“…[Hosseinabady and Nunez-Yanez 2010] reported a modest speed-up of 38% with no loss of accuracy by using lightweight schedulers that handle the time reference for a group of tasks. In [Eggenberger and Radetzki 2013], the authors propose a decomposition approach that breaks the simulation kernel in multiple threads that can be executed in parallel with a lightweight time synchronisation between then. By running the decomposed kernel over a 16-core machine, the authors were able to obtain a speed-up of up to 15.5x, also without any loss of accuracy.…”

Section: Related Workmentioning

confidence: 99%

Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration

Indrusiak

Harbin

Santos

2015

ACM Trans. Des. Autom. Electron. Syst.

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An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this paper, we identify a time-predictable network-on-chip architecture and we show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1000 times faster when compared to a cycle-accurate model of the same interconnect.

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“…al. [7] explain performance different memory architecture and management in an NoC platform. As most of the available multicore simulators like Multi2sim [30], SESC [25], SimicGems [20], and, etc are very slow.…”

Section: Previous Workmentioning

confidence: 99%

Bufferless NOC Simulation of Large Multicore System on GPU Hardware

Kumar¹,

Sahu²

2015

Preprint

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Last level cache management and core interconnection network play important roles in performance and power consumption in multicore system. Large scale chip multicore uses mesh interconnect widely due to scalability and simplicity of the mesh interconnection design. As interconnection network occupied significant area and consumes significant percent of system power, bufferless network is an appealing alternative design to reduce power consumption and hardware cost. We have designed and implemented a simulator for simulation of distributed cache management of large chip multicore where cores are connected using bufferless interconnection network. Also, we have redesigned and implemented the our simulator which is a GPU compatible parallel version of the same simulator using CUDA programming model. We have simulated target large chip multicore with up to 43,000 cores and achieved up to 25 times speedup on NVIDIA GeForce GTX 690 GPU over serial simulation.

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Scalable parallel simulation of networks on chip

Cited by 11 publications

References 15 publications

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration

Bufferless NOC Simulation of Large Multicore System on GPU Hardware

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