Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration

Abstract

An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this paper, we identify a time-predictable network-on-chip architecture and we show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1000 times faster when compared to a cycle-accurate model of the same interconnect.

Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip

“…This The simulation framework used for this section is a cycleaccurate NoC model with support for priority preemption and virtual channels. This simulator has been extensively validated in our previous work, frequently being used as a baseline for results in latency and power analysis [11] [8].…”

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

“…The TLM-PRE TLM preemptive model presented in this section is described more fully in [4], [5] and [29]. The goal of the algorithm is to simulate a priority preemptive NoC with a greatly reduced frequency of events.…”

Speed and accuracy dilemma in NoC simulation: What about memory impact?

“…In this work we restrict the NoCs to be simulated to NoCs with priority preemptive virtual channels. It allows to simulate the NoC 1000 times faster with more than 90% of accuracy [8], [9]. Horsinka et al [10] also proposed a TLM NoC simulator integrated in a multi-level simulation framework.…”

“…The McSim-TLM simulator is based on existing work [9] and has been implemented in SystemC. To speedup simulations of such NoC architectures we rely on the fact that a packet with high priority will always preempt a packet with lowest priority.…”

“…The number of these false conflicts mainly depends on the NoC size and the packet length. In the opposite way, the assumption about using the entire route all the time can also lead to scenarios where the simulator ignores some conflicts occurring in practice [9].…”