Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Abstract

Article:Harbin, James orcid.org/0000-0002-6479-8600 and Soares Indrusiak, Leandro orcid.org/0000-0002- 9938-2920 (2016) AbstractThe simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of stateof-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput and latency performance of the system. This paper presents a series of network-on-chip transaction-level model (TLM) algorithms that provide a highly abstracted view of the process of data transmission in priority preemptive and non-preemptive networks-on-chip, which permit a major reduction in simulation event count. These simulation models are tested using two realistic application case studies and with synthetic traffic. Results presented demonstrate that these lightweight TLM simula- * Corresponding author: Telephone +44 (0) tion models can produce latency figures accurate to within mere flits for the majority of flows, and more than 93% accurate link dynamic power consumption modelling, while simulating 2.5 to 3 orders of magnitude faster when compared to a cycle-accurate model of the same interconnect.

Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip

“…Random XY/YX is a randomised version of pseudo-adaptive XY routing used in [4], so the route of the packet to its destination is randomly chosen between the XY or the YX route prior to the injection of the packet header into the network. In random west-first, we randomise one of the turn model routing 8 [7] so that whenever a packet is allowed more than one route it randomly chooses one of them (i.e. uniform probability among all alternatives).…”

“…This The simulation framework used for this section is a cycleaccurate NoC model with support for priority preemption and virtual channels. This simulator has been extensively validated in our previous work, frequently being used as a baseline for results in latency and power analysis [11] [8].…”

Side-channel protected MPSoC through secure real-time networks-on-chip

“…The simulation framework used for this section is a cycle-accurate NoC model with support for priority preemption and virtual channels. This simulator has been extensively validated in our previous work, frequently being used as a baseline for results in latency and power analysis [37] [38].…”