Scalable I/O architecture for buses

James, D.V.

doi:10.1109/cmpcon.1989.301990

Cited by 8 publications

(1 citation statement)

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“…This interconnect also supports live insertion and withdrawal, and may be able to implement request-combining schemes to reduce the effect of congestion at hot spots. 3 The command word of the header controls packet flow and interconnect access. Priority arbitration is supported with round robin arbitration on the lowest level.…”

Section: Figures Switch Interconnectmentioning

confidence: 99%

Scalable coherent interface

Gustavson¹

Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage

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The Scalable Coherent Interface (IEEE P1596) is establishing an interface standard for very high performance multiprocessors, supporting a cache-coherent-memory model scalable to systems with op to 64K nodes. This Scalable Coherent Interface (SCI) will supply a peak bandwidth per node of 1 GigaByte/second. The SCI standard should facilitate assembly of processor, memory, I/O and bus bridge cards from multiple vendors into massively parallel systems with throughput far above what is possible today.The SCI standard encompasses two levels of interface, a physical level and a logical level. The physical level specifles electrical, mechanical and thermal characteristics of connectors and cards that meet the standard. The logical level describes the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives and error recovery. In this paper we address logical level issues such as packet formats, packet transmission, transaction handshake, flow control, and cache coherence.

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Section: Figures Switch Interconnectmentioning

confidence: 99%

Scalable coherent interface

Gustavson¹

Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage

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Applications for the scalable coherent interface

Gustavson¹

1990

AIP Conference Proceedings

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IEEE P1596, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x) and other modern high-performance buses. SC1 goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for bridges which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. This paper reports the status of the work in progress and suggests some applications in data acquisition and physics.

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The Scalable Coherent Interface, IEEE P 1596, status and possible applications to data acquisition and physics

Gustavson

1990

IEEE Trans. Nucl. Sci.

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IEEE PI596, the Scalable Coherent Interface (formerly known as SupcrBus) is based on experience sained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), FuUirebus (IEEE P896.x) and outer modem 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent disrributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. This paper presents a summary of current directions, reports the status of the work in progress, and suggests some applications in data acquisition and physics.

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Scalable I/O architecture for buses

Cited by 8 publications

References 0 publications

Scalable coherent interface

Scalable coherent interface

Applications for the scalable coherent interface

The Scalable Coherent Interface, IEEE P 1596, status and possible applications to data acquisition and physics

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