The Scalable Coherent Interface, IEEE P 1596, status and possible applications to data acquisition and physics

Abstract

IEEE PI596, the Scalable Coherent Interface (formerly known as SupcrBus) is based on experience sained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), FuUirebus (IEEE P896.x) and outer modem 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent disrributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. This paper presents a summary of current directions, reports the status of the work in progress, and suggests some applications in data acquisition and physics.