The Scalable Coherent Interface (IEEE P1596) is establishing an interface standard for very high performance multiprocessors, supporting a cache-coherent-memory model scalable to systems with op to 64K nodes. This Scalable Coherent Interface (SCI) will supply a peak bandwidth per node of 1 GigaByte/second. The SCI standard should facilitate assembly of processor, memory, I/O and bus bridge cards from multiple vendors into massively parallel systems with throughput far above what is possible today.The SCI standard encompasses two levels of interface, a physical level and a logical level. The physical level specifles electrical, mechanical and thermal characteristics of connectors and cards that meet the standard. The logical level describes the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives and error recovery. In this paper we address logical level issues such as packet formats, packet transmission, transaction handshake, flow control, and cache coherence.
With the ANSIAEEE Std 1596-1 992 Scalable Coherent Interface (SCI), a few or many processors can share cached data in a coherent fashion (i.e. their caches are transparent to software). Scalability constrains the protocols to rely on simple request-response protocols, rather than the eavesdrop or 3-party transactions assumed by (unscalable) bus-based systems.The linear nature of the base SCI protocols limits their performance when data is being actively shared by large numbers of processors. To meet these needs, the IEEE P1596.2 working group is currently dejining a compatible set of extensions based on distributed binary trees. Scalabiliry includes optionality: simple a d o r specialized noncoherent systems are not affected by the costs of coherence protocols.
The Scalable Coherent Interface standard defines a new generation of interconnection that spans the full range from supercomputer memory 'bus' to campus-wide network.SCI provides bus-like services and a shared-memory software model while using an underlying packet protocol on many independent communication links. Initially these links are 1 GByte/s (wires) and 1 GBit/s (fiber), but the protocol scales well to future faster or lower-cost technologies. The interconnect may use switches, meshes, and rings.The SCI distributed-shared-memory model is simple and versatile, enabling for the first time a smooth integration of highly parallel multiprocessors, workstations, personal computers, VO, networking and data acquisition.
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