Distributed-directory scheme: scalable coherent interface

James, D.V.; Laundrie, A.T.; Gjessing, Stein; Sohi, Gurindar S.

doi:10.1109/2.55503

Cited by 130 publications

(14 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover, it requires multiple accesses to the directory memory when the number of processors exceeds the width of a single access. Although the use of a chained directory [11,23] decreases the directory size, it also results in the inefficiency of multiple accesses.…”

Section: Related Workmentioning

confidence: 99%

Lightweight hardware distributed shared memory supported by generalized combining

Tanaka

Matsumoto

Hiraki

1999

Proceedings Fifth International Symposium on High-Performance Computer Architecture

View full text Add to dashboard Cite

On a large-scale parallel computer system, shared memory provides a general and convenient programming environment. This paper describes a lightweight method for constructing an efficient shared memory system supported by hierarchical coherence management and generalized combining. The hierarchical management technique and generalized combining cooperate with each other. We eliminate the following heavyweight and high-cost factors: a large amount of directory memory which is proportional to the number of processors, a separate memory component for the directory, tag/state information, and a protocol processor. In our method, the amount of memory required for the directory is proportional to the logarithm of the number of processors. This implies that a single word for each memory block is sufficient for covering a massively parallel system and that the access costs of the directory are small. Moreover, our combining technique, generalized combining, does not expect the accidental events which existing combining networks do, that is, events that messages meet each other at a switching node. A switching node can combine succeeding messages with a preceding one even after the preceding message leaves the node. This can increase the rate of successful combining. We have developed a prototype parallel computer, OCHANOMIZ-5, that implements this lightweight distributed shared memory and generalized combining with simple hardware. The results of evaluating the prototype's performance using several programs show that our methodology provides the advantages of parallelization.

show abstract

Section: Related Workmentioning

confidence: 99%

Lightweight hardware distributed shared memory supported by generalized combining

Tanaka

Matsumoto

Hiraki

1999

Proceedings Fifth International Symposium on High-Performance Computer Architecture

View full text Add to dashboard Cite

show abstract

“…Each processing node is an Intel Quad bus-based SMP with four Pentium Pro processors. The customized interconnection board implements the scalable coherence interface (SCI) directory protocol [18].…”

Section: Related Workmentioning

confidence: 99%

Optimizing operating system performance for CC‐NUMA architectures

Chang

2003

Concurrency and Computation

View full text Add to dashboard Cite

SUMMARYThe CC-NUMA (cache-coherent non-uniform memory access) architecture is an attractive solution to scalable servers. The performance of a CC-NUMA system heavily depends on the number of accesses to remote memory through an interconnection network. To reduce the number of remote accesses, an operating system needs to exploit the potential locality of the architecture. This paper describes the design and implementation of a UNIX-based operating system supporting the CC-NUMA architecture. The operating system implements various enhancements by revising kernel algorithms and data structures. This paper also analyzes the performance of the enhanced operating system by running commercial benchmarks on a real CC-NUMA system. The performance analysis shows that the operating system can achieve improved performance and scalability for CC-NUMA by implementing kernel data striping, localization and load balancing.

show abstract

“…Cache coherence protocols have been proposed that uses linkedlists to track sharers in a multi-processor system [13,17]. Although sharers are also tracked using pointers in Proximity Coherence, our Normalized estimated network energy consumption compared to a system using the MESI baseline protocol.…”

Section: Related Workmentioning

confidence: 99%

Proximity coherence for chip multiprocessors

Barrow-Williams

Fensch

Moore

2010

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques

View full text Add to dashboard Cite

Many-core architectures provide an efficient way of harnessing the increasing numbers of transistors available in modern fabrication processes. While they are similar to multi-node systems, they exhibit different communication latency and storage characteristics, providing new design opportunities that were previously not feasible. Traditional cache coherence protocols, although often used in many-core designs, have been developed in the context of multinode systems. As such, they seldom take advantage of the new possibilities that many-core architectures offer.We propose Proximity Coherence, a scheme in which L1 load misses are optimistically forwarded to nearby caches via new dedicated links rather than always being indirected via a directory structure. Such an optimization is made possible by the comparable cost of local cache accesses with the use of on-chip network resources. Coherency is maintained using lightweight graph structures embedded in the L1 caches. We compare our Proximity Coherence protocol to an existing directory-based MESI protocol using fullsystem simulations of a 32 core system. Our extension lowers the latency of L1 cache load misses by up to 32% while reducing the bytes transferred on the global on-chip interconnect by up to 19% for a range of parallel benchmarks. Employing Proximity Coherence provides execution time improvements of up to 13%, reduces cache hierarchy energy consumption by up to 30% and delivers a more efficient solution to the challenge of coherence in chip multiprocessors.

show abstract

Distributed-directory scheme: scalable coherent interface

Cited by 130 publications

References 1 publication

Lightweight hardware distributed shared memory supported by generalized combining

Lightweight hardware distributed shared memory supported by generalized combining

Optimizing operating system performance for CC‐NUMA architectures

Proximity coherence for chip multiprocessors

Contact Info

Product

Resources

About