S/390 Parallel Enterprise Server Generation 3: A balanced system and cache structure

Abstract

Since initiating the information technology industry-wide transition from bipolar to CMOS technology with the first generation of S/390@ processors in 1994, IBM reached another major milestone with the introduction of the third generation in September 1996. The balanced system and cache structure and the modularity of the components of Generation 3 support a wide performance range from a uniprocessor to a high-performance multiprocessing system. Because of this modularity, Generation 4 is also based on this structure.

Shared-cache clusters in a system with a fully shared memory

“…When fetch data must replace an existing cache entry, the line being replaced must be written back to main memory if it has been modified. Two mechanisms are available-LS/LF [1], and conditional line store (CLST)-for casting out the "old" line with minimal performance impact. The method used is dependent upon the availability of the data being stored relative to the completion of bus arbitration for the fetch request.…”

“…As described by Getzlaff et al [1], the S/390 Parallel Enterprise Server Generation 3 (G3) features a system structure which supports microprocessor and system frequencies in excess of 160 MHz. This design features conventional, dedicated LI and L2 caches as well as a novel, shared L2.5 cache [2] which services all of the microprocessors in the system.…”

“…Finally, during the design of the S/390 G3 system, it became apparent that a large symmetric multiprocessor introduced unwanted packaging complexity on the bus connections among the various system components. This last challenge was solved on the S/390 G3 system by distributing four microprocessors' private L2s across four SRAM cache chips [1].…”

“…Command and address information is transmitted in the same cycle, while data are sent in subsequent cycles. Because of relatively long memory DRAM access times, the individual memory cards are organized into two independent banks [1]. Consequently, the BSN bus is logically interleaved to take advantage of this, allowing two separate commands to the memory subsystem to be active simultaneously on each bus (meaning that there can be up to eight active memory operations across the four BSNs in any cycle).…”

Run-control migration from single book to multibooks

“…Previous zSeries* systems, G3 to G6, were limited to one book [1][2][3][4]. The clock chip-which provides functions to support the chips of a book during setup of the entire system and also support functions in a running environment-is the central point of the hardwareimplemented run-control structure.…”