Since initiating the information technology industry-wide transition from bipolar to CMOS technology with the first generation of S/390@ processors in 1994, IBM reached another major milestone with the introduction of the third generation in September 1996. The balanced system and cache structure and the modularity of the components of Generation 3 support a wide performance range from a uniprocessor to a high-performance multiprocessing system. Because of this modularity, Generation 4 is also based on this structure.
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This prototype of a processor chip set with a mainframe archi tecture* is implemented using 5 CMOS standard cell-chips. High performance is achieved by wide busses and a RISC-like imple mentat ion of frequently-used instructions.The Chip Set consists of 4 units:(1) The instruction processor chip fetches and decodes the in structions, and contains the microcode storage. 75 general and 54 floating.point instructions are controlled directly by hard ware; (2) The cache chips contain the address translation for up to 19 virtual address spaces, a 4-way set·associative 16kB datal instruction cache, and a 32B instruction-buffer, whi ch is loaded 16B per cycle from the cache; (3) The fixed-point proce ssor chip contains the fixed-poillt registers and arithmetic and a second adder for the address calcul ation (base + displacement + index);(4) The floating-point processor chip contains the f1oating.point registers, multiplier and arithmetic unit. (Figure 1)The processor is based on a 4·stage pipeline (.5 stages for floating-point instructions). Most RR instruction s, including floating-point, and many RX instructions are executed in a single cycle. Branches require a single cycle if not taken, and 2 cycles otherwise. The cycles-per-instruction average for simple instruc tion mixes, as found in Dhrystone, is 1.4, including the cache miss overhead. (Figure 2) All RAM. and data.paths, both internal and external, are parity-checked. All logic is designed according to LSSD.rules and supports self test.A two-phase clock is distributed to all chips. The LSSD master and slave-clocks are generated on· chip and distributed by load-balanced power trees. Skew between the falling edge of the master clock and the rising edge oj' the slave clock between any two latches is below 0. 5ns for the same chip and 2ns for differ ent chips.The l.OJ.lm technology used for this proce ssor is based on a CMOS n-well process with 3 metal layers and typical circnit dr· lay of O.4ns per gate, due to the O . .5J.lm channd length and an oxide thickness of 13.'iA. To achieve high reliability, th(, supply voltage must be lowered to 3.6 VI. The reduced voltage does not allov. full capitalization on the reduced transistor dimensions. but contributes to red uction in power dissipation. The typical machine cycle time at 3.6 V and 250 C is 20ns, including paths totally on chip and with both on· and off.chip connect. (Tables 1,2)The design is a combination of sea of gates (SOG) and standanl cell techniques. The channelless wiring methodology i, ha,ed on SOG. The circuit library is similar to a reduced standard cell library consisting of ;'\lAND, AND, XOR and, shift· register circuits. The design of the circuits is such that most of the area on top of the circuits is clear and free for global wiring. 50-.199(NEEElhwrn'ittiunatSolid-State Circuits Conference 8 different macros are required for this chipset. The main emphasis is on high performance, multi·usage on the chip, and embedding t1exibility. One group of array macros is the clocked 6-device static RAM's. The...
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