Verification of tlie S/390® Parallel EnterpriseServer G4 processor and level 2 cache (L2) chips was performed using a different approach than previously. This paper describes the methods employed by our functional verification team to demonstrate that its logical system complied with the S/390 architecture while staying within the changing cost structure and time-to-market constraints. Verification proceeded at four basic levels defined by the breadth of logic being tested. The lowest level, designer macro verification, contained a single designer's hardware description language (in VHDL). Unit-level verification consisted of a logical portion of function that generally contained four or five designers' logic. The third level of verification was the chip level, in which the processor or L2 chips were individually tested. Finally, system-level verification was performed on symmetric multiprocessor (SMP) configurations that included bus-switching network (BSN) chips and I/O connection chips, designated as memory bus adaptors (MBAs), along with multiple copies of the processor and L2 chips.
Recent advances in technology, computer architecture, and automated design environments have ushered in a new era of computer design in which large complex servers such as the S/390 G5 Parallel Enterprise Server™ can be delivered with times to market once reserved for low-end systems such as single-user workstations and personal computers. Yet, the time to market is inversely proportional to customer demand for reliable and continuously available systems. Therefore, the need exists to build and simulate a complete system which incorporates realistic and accurate behavioral representations for all design components. This paper describes a method for modeling an analog phase-locked loop, interfacing it with digital sequential logic components, and simulating the entire system in a high-performance two-cycle simulation environment. Further discussion demonstrates the role this verification has played in the deployment of an improved design point with a shorter time to market compared to previous generations of S/390 ® CMOS machines.
This paper describes the migration of the hardwareimplemented run-control functions from a single-book structure with one flexible service processor (FSP) and one service element (SE) per system to a multibook structure with one FSP per book and one SE per system. The new system structure required two new interfaces between the clock chips on the different books. The first interface is required for dynamic configuration data exchange between books. The alternative path via the SE would not meet the performance requirements. This interface is available in the initial millicode load flow before the L2 caches with their ring structure are operational. Another requirement is the necessity of starting and stopping all books synchronously. The second additional interface between the clock chips on different books enables this function. Nevertheless, the hardware implementation is so flexible that each book may operate independently of the other books. The clock chips are connected as a peer-to-peer network, so no special master is necessary in the system.
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