Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

Abstract

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔV th, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness t D and barrier thickness t B, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔN it, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔN it is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation

Modeling small-signal response of GaN-based metal-insulator-semiconductor high electron mobility transistor gate stack in spill-over regime: Effect of barrier resistance and interface states

“…1(c)). Due to existing V th instabilities and interlinking of ac response and slow drifts, 9,15 the voltage sweep was performed several times for each frequency for the same starting biasing conditions and same time between the measurements. Thus some typical behavior with quasi-stable hysteresis was repeatedly observed in CV curves for particular frequency.…”

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

“…A first type focuses on the analysis of the V TH drift during stress. [3][4][5] In contrast, a second type focuses on the characterization of the quality of the gate dielectrics in terms of interface states and border traps on the fresh devices [6][7][8][9] without discussing the implications on V TH instability during operations. The link between these two type of analyses is still unclear.…”

“…1 However, the threshold voltage (V TH ) instability of MIS-HEMTs remains a critical issue. Especially, V TH hysteresis after a positive gate voltage sweep and V TH shift during a positive bias gate stress [2][3][4][5] are important reliability challenges. Therefore, it is important to understand the origin of V TH shift in order to provide technology solutions to minimize these instability issues.…”

Investigation of AlGaN/GaN HEMTs degradation with gate pulse stressing at cryogenic temperature

“…V th shift) are induced by positive gate voltage, suggesting the presence of traps between AlGaN barrier and dielectric under the gate. [10][11][12][13] Lagger et al 14 discuss the impact of a different dielectric material (LPCVD SiN, SiO 2 , Al 2 O 3 , HfO 2 , and HfSiO 2 ) and thickness on the V th shift and on the density of trapped electrons N it , when a forward gate bias stress is performed. Liu et al estimated accurately the state density of traps at the LPCVD-SiNx/III-nitride interface by adopting fast transfer I-V and multifrequency C-V at room temperature.…”