Modeling small-signal response of GaN-based metal-insulator-semiconductor high electron mobility transistor gate stack in spill-over regime: Effect of barrier resistance and interface states

Abstract

We provide theoretical and simulation analysis of the small signal response of SiO 2 /AlGaN/GaN metal insulator semiconductor (MIS) capacitors from depletion to spill over region, where the AlGaN/SiO 2 interface is accumulated with free electrons. A lumped element model of the gate stack, including the response of traps at the III-N/dielectric interface, is proposed and represented in terms of equivalent parallel capacitance, C p , and conductance, G p . C p -voltage and G p -voltage dependences are modelled taking into account bias dependent AlGaN barrier dynamic resistance R br and the effective channel resistance. In particular, in the spill-over region, the drop of C p with the frequency increase can be explained even without taking into account the response of interface traps, solely by considering the intrinsic response of the gate stack (i.e., no trap effects) and the decrease of R br with the applied forward bias. Furthermore, we show the limitations of the conductance method for the evaluation of the density of interface traps, D it , from the G p /x vs. angular frequency x curves. A peak in G p /x vs. x occurs even without traps, merely due to the intrinsic frequency response of gate stack. Moreover, the amplitude of the G p /x vs. x peak saturates at high D it , which can lead to underestimation of D it . Understanding the complex interplay between the intrinsic gate stack response and the effect of interface traps is relevant for the development of normally on and normally off MIS high electron mobility transistors with stable threshold voltage. V C 2015 AIP Publishing LLC. [http://dx.

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

“…13 Fig. 4 14 indicates that the conventional conductance measurement could underestimate the interface states value. For this reason, two additional electrical evaluations were used: AC-g m dispersion 8,15 and the V TH shift during a positive gate bias stress.…”

AC-Capacitance Techniques for Interface Trap Analysis in GaN-Based Buried-Channel MIS-HEMTs

“…Recently, we adopted ac-conductance method to characterize the interface traps in Al 2 O 3 (AlN NIL)/GaN MOSC diode (without barrier layer in the gate region) with the same gate dielectric stack process as described in this paper [26]. Similar D it 's ranges in MIS and MOSC diodes extracted, respectively, using ac-capacitance and ac-conductance techniques further validate the effectiveness of ac-capacitance method for interface trap mapping in practical III-N MIS heterostructures, suggesting that ac response of interface traps can make primary contribution to the f /T -dispersions in ac-CV characteristics as long as D it is not extremely low [8].…”

“…It is because a high density of interface traps at a low-quality interface could pin the Fermi level at a deep level, at which the filling/emission processes of interface traps cannot respond to the ac measurement signal, impeding the presence of second rising slope in the measured ac-CV characteristics of III-N MIS heterostructures. Recently, Capriotti et al [8] reported that the ac response of interface traps and the barrier layer could result in comparable effects on the second rising slope when the interface trap density is extremely low (in the order of 10 11 cm −2 ), but the ac response of interface trap still dominates over that of barrier layer as long as interface trap density is higher, which is the case for most III-N MIS heterostructures to date. To explain the physical mechanisms of the second slope in ac-CV characteristics, the response of interface traps to the ac measurement signal v ac need to be analyzed.…”

“…First, the wide bandgap nature of III-N materials results in long emission time constant (τ e ) of relatively deep interface traps, limiting the detectable energy depth at room temperature (RT). Moreover, unlike MOS structures in which the dielectric/semiconductor interface is located at the channel, buried-channel III-N MIS heterostructures have two interfaces (the dielectric/III-N and the III-N hetero-interface) with the critical dielectric/III-N interface spatially separated from the 2DEG channel by the barrier layer, adding complication in interface trap extraction in III-N MIS heterostructures [7], [8].…”

Interface Si donor control to improve dynamic performance of AlGaN/GaN MIS-HEMTs

“…21,[25][26][27] The method reported by Yang et al 27 f -dispersions of the second slope onset (V ON ) in the ac-CV characteristics (Fig. 2), the interface-state density of LPCVD-SiN x /GaN-cap/AlGaN was calculated by…”