The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔV th, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness t D and barrier thickness t B, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔN it, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔN it is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation
We provide theoretical and simulation analysis of the small signal response of SiO 2 /AlGaN/GaN metal insulator semiconductor (MIS) capacitors from depletion to spill over region, where the AlGaN/SiO 2 interface is accumulated with free electrons. A lumped element model of the gate stack, including the response of traps at the III-N/dielectric interface, is proposed and represented in terms of equivalent parallel capacitance, C p , and conductance, G p . C p -voltage and G p -voltage dependences are modelled taking into account bias dependent AlGaN barrier dynamic resistance R br and the effective channel resistance. In particular, in the spill-over region, the drop of C p with the frequency increase can be explained even without taking into account the response of interface traps, solely by considering the intrinsic response of the gate stack (i.e., no trap effects) and the decrease of R br with the applied forward bias. Furthermore, we show the limitations of the conductance method for the evaluation of the density of interface traps, D it , from the G p /x vs. angular frequency x curves. A peak in G p /x vs. x occurs even without traps, merely due to the intrinsic frequency response of gate stack. Moreover, the amplitude of the G p /x vs. x peak saturates at high D it , which can lead to underestimation of D it . Understanding the complex interplay between the intrinsic gate stack response and the effect of interface traps is relevant for the development of normally on and normally off MIS high electron mobility transistors with stable threshold voltage. V C 2015 AIP Publishing LLC. [http://dx.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.