Review of Silicon Photonics Foundry Efforts

Lim, Andy Eu-Jin; Song, Jun-Feng; Qing, Feng‐Ling; Li, Chao; Tu, Xiaoguang; Duan, Ning; Chen, Kok Kiong; Tern, Roger Poh-Cher; Liow, Tsung-Yang

doi:10.1109/jstqe.2013.2293274

Cited by 327 publications

(177 citation statements)

References 24 publications

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“…In particular, we increased the nominal CD to 120 nm and 150 nm, for the continuously apodized coupler. These dimensions are typically accepted by the silicon photonics foundries using 193 nm DUV lithography [6,10,11,13]. As can be observed in Figs.…”

Section: Coupler Apodizationmentioning

confidence: 91%

“…Using Si waveguide layers thicker than 220 nm generally results in a substantially increased grating directionality [3,8,11,12]. However, the SOI with 220-nm-thick silicon presently dominates in multi project wafer (MPW) shuttles, offered by the publicly accessible silicon photonic foundries [10,13]. To date, the state-of-the-art solutions to maximize the grating directionality exploit comparatively complex structures [14][15][16][17][18][19][20][21][22][23][24][25], including backside wafer processing and metal mirror deposition [14][15][16][17], or bonding dielectric mirrors [3,6,7,[18][19][20].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Single-etch subwavelength engineered fiber-chip grating couplers for 13 µm datacom wavelength band

Benedikovič¹,

Alonso-Ramos²,

Cheben³

et al. 2016

Opt. Express

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Vous avez des questions? Nous pouvons vous aider. Pour communiquer directement avec un auteur, consultez la première page de la revue dans laquelle son article a été publié afin de trouver ses coordonnées. Si vous n'arrivez pas à les repérer, communiquez avec nous à PublicationsArchive-ArchivesPublications@nrc-cnrc.gc.ca. Questions? Contact the NRC Publications Archive team atPublicationsArchive-ArchivesPublications@nrc-cnrc.gc.ca. If you wish to email the authors directly, please see the first page of the publication for their contact information. NRC Publications Archive Archives des publications du CNRCThis publication could be one of several versions: author's original, accepted manuscript or the publisher's version. / La version de cette publication peut être l'une des suivantes : la version prépublication de l'auteur, la version acceptée du manuscrit ou la version de l'éditeur. For the publisher's version, please access the DOI link below./ Pour consulter la version de l'éditeur, utilisez le lien DOI ci-dessous. Abstract:We report, for the first time, on the design and experimental demonstration of fiber-chip surface grating couplers based on subwavelength grating engineered nanostructure operating in the low fiber chromatic dispersion window (around 1.3 m wavelengths), which is of great interest for short-reach data communication applications. Our coupler designs meet the minimum feature size requirements of large-volume deepultraviolet stepper lithography processes. The fiber-chip couplers are implemented in a standard 220-nm-thick silicon-on-insulator (SOI) platform and are fabricated by using a single etch process. Several types of couplers are presented, specifically the uniform, the apodized, and the focusing designs. The measured peak coupling efficiency is −2.5 dB (56%) near the central wavelength of 1.3 m. In addition, by utilizing the technique of the backside substrate metallization underneath the grating couplers, the coupling efficiency of up to −0.5 dB (89%) is predicted by Finite Difference Time Domain (FDTD) calculations. 4190-4193 (2015).

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Section: Coupler Apodizationmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

Single-etch subwavelength engineered fiber-chip grating couplers for 13 µm datacom wavelength band

Benedikovič¹,

Alonso-Ramos²,

Cheben³

et al. 2016

Opt. Express

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“…Coupling the optical ports to the interposer will necessitate passive photonics elements such as couplers and waveguides on the interposer itself. To enable such elements, the silicon interposer will have to include SOI cross sections similar to the ones supported by the 2D Si photonics platforms of IBM [89], STMicroelectronics [90], or IME [91].…”

Section: Photonics Integrationmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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“…Deviations between design and experiments point to the need for further investigations of the minimum feature dimensions. Foundry fabricated silicon (Si) photonics seek to implement highly sophisticated photonic integrated circuits (PICs) at low cost by using the mature manufacturing process of microelectronics [1][2][3]. The high refractive index contrast in Si photonic platforms not only allows for compact device footprints but also makes possible device concepts that can take advantage of the strong optical confinement and scattering (e.g., grating couplers, micro-resonators, photonic crystals) [4][5][6].…”

mentioning

confidence: 99%

Binary particle swarm optimized 2 × 2 power splitters in a standard foundry silicon photonic platform

et al. 2016

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Compact power splitters designed ab initio using binary particle swarm optimization in a 2D mesh for a standard foundry silicon photonic platform are studied. Designs with a 4.8 μm × 4.8 μm footprint composed of 200 nm × 200 nm and 100 nm × 100 nm cells are demonstrated.Despite not respecting design rules, the design with the smaller cells had lower insertion losses and broader bandwidth and showed consistent behavior across the wafer. Deviations between design and experiments point to the need for further investigations of the minimum feature dimensions. Foundry fabricated silicon (Si) photonics seek to implement highly sophisticated photonic integrated circuits (PICs) at low cost by using the mature manufacturing process of microelectronics [1][2][3]. The high refractive index contrast in Si photonic platforms not only allows for compact device footprints but also makes possible device concepts that can take advantage of the strong optical confinement and scattering (e.g., grating couplers, micro-resonators, photonic crystals) [4][5][6]. The growing availability of foundry Si photonics, in combination with expanded computation capabilities for detailed electromagnetic simulations, open the opportunity to explore device designs that cannot be implemented in traditional, lower index contrast PIC platforms such as silica and compound semiconductors and are yet volume manufacturable.Device design performed by topology optimization without any a priori assumptions on the geometry has recently generated much interest [7][8][9][10]. As opposed to conventional design methodologies in which a few critical geometric parameters are tuned on a fixed geometry, topology optimization can find unexpected solutions with good performance within demanding constraints by exploring much larger parameter spaces. An example is the polarization beam splitter of [9], which had a design footprint constraint of 2.4 μm × 2.4 μm. However, usual optimization approaches (e.g., in [8][9][10]) rely on highresolution rendering of intricate geometric features, such as through electron-beam lithography, which can result in designs that are incompatible with the design rules and minimum feature sizes in foundry processes, which use deep ultraviolet (DUV) photolithography.In this Letter, we investigate foundry fabrication of an optimization designed 2 × 2 3 dB power splitter. Power splitters are a common building block in PICs and, in Si photonic platforms, are typically implemented as multimode interference (MMI) couplers, directional couplers, and adiabatic couplers. Typical footprints in a standard Si photonic platform have footprints around 39 μm × 5.2 μm for a 3 dB directional coupler and 158 μm × 4.1 μm for an MMI coupler [11]. Because power splitters may be instantiated many times in a PIC, a size reduction of the 2 × 2 splitter can save substantial circuit area. Here, we explore the design and implementation of 2 × 2 power splitters with a footprint constraint of 4.8 μm × 4.8 μm designed through optimization that accounted for the minimum ...

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Review of Silicon Photonics Foundry Efforts

Cited by 327 publications

References 24 publications

Single-etch subwavelength engineered fiber-chip grating couplers for 13 µm datacom wavelength band

Single-etch subwavelength engineered fiber-chip grating couplers for 13 µm datacom wavelength band

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Binary particle swarm optimized 2 × 2 power splitters in a standard foundry silicon photonic platform

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