Retracted: Power macro‐modeling technique for NoC‐based homogeneous layered 3D ICs

Durrani, Yaseer Arafat

doi:10.1002/jnm.2309

Cited by 2 publications

(3 citation statements)

References 12 publications

(13 reference statements)

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“…The power modeling approach of BFT network is discussed in this section. The proposed model further improves these techniques, in the electrical characteristics of the network, and most of the model equations are modified as described below.…”

Section: Power Modeling Methodology For 3d Icmentioning

confidence: 99%

“…An interesting comparison of power consumption, area, throughput, and the latency among major NoC topologies is presented in Kumar et al This work is used for the trade‐off of different topologies to provide better latency and throughput at the cost of high‐power dissipation and large area. Some researchers have analyzed in Durrani and Elmiligi et al that the latency and power dissipation for fat tree, mesh, and torus network architectures may be used in digital image processing applications to generate workloads. Other researchers have compared mesh, spidergon, and ring topologies under uniform traffic patterns.…”

Section: Related Workmentioning

confidence: 99%

“…In NoC, the routers are the main bottleneck in bandwidth and power dissipation, which has been addressed in this paper. The advanced technique introduced in Durrani uses a 3D NoC analytical model on a reroute formulation for routing flows for power optimization of the network. Their results deliver the power and performance improvements over the regular 3D mesh implementations.…”

Section: Related Workmentioning

confidence: 99%

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Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs

Durrani

2018

Int J Numerical Modelling

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Low‐power consumption and heat dissipation are becoming serious issues in the design process of the 3D integrated circuit (IC). The multiple dies are stacked and communicated through‐silicon vias to work as a single device to achieve high performance with minimum power and heat dissipation. This paper presents the power and thermal modeling approaches for the power/heat estimation of homogenous integration of network‐on‐chip‐based tree architecture in 3D IC design. The preliminary experimental work of power model is divided in 2 major parts of the design. The first part estimates the power of network‐on‐chip tree architecture on each stack/layer separately, and the second estimates the power dissipation of the uniformly distributed through‐silicon vias and input/output pads. The model uses a linear function to estimate the average power dissipation. The thermal model estimates the heat dissipation by using thermal sensors on different sections of the individual layer. For an entire IC design, the average power/thermal is extracted by simple addition of all power/thermal estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 16.29%.

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Section: Power Modeling Methodology For 3d Icmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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