Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs

Abstract

Low‐power consumption and heat dissipation are becoming serious issues in the design process of the 3D integrated circuit (IC). The multiple dies are stacked and communicated through‐silicon vias to work as a single device to achieve high performance with minimum power and heat dissipation. This paper presents the power and thermal modeling approaches for the power/heat estimation of homogenous integration of network‐on‐chip‐based tree architecture in 3D IC design. The preliminary experimental work of power model is divided in 2 major parts of the design. The first part estimates the power of network‐on‐chip tree architecture on each stack/layer separately, and the second estimates the power dissipation of the uniformly distributed through‐silicon vias and input/output pads. The model uses a linear function to estimate the average power dissipation. The thermal model estimates the heat dissipation by using thermal sensors on different sections of the individual layer. For an entire IC design, the average power/thermal is extracted by simple addition of all power/thermal estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 16.29%.

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

“…One of the most important concerns in the power macro-modeling is the choice of the model’s input parameters. They should capture the primary features that are responsible for the system’s power dissipation and thus it can have good accuracy in its power estimates [ 24 , 25 ]. We will focus on our problem of statistical power macro-modeling for IP-based 3D digital systems.…”

Electrical modeling of carbon nanotube‐based shielded through‐silicon vias for three‐dimensional integrated circuits

“…As a potential candidate to meet high performance and miniaturization of next-generation electronics, threedimensional integrated circuits (3D ICs) have attracted intense interests of research in recent years. [1][2][3] Through-silicon via (TSV), a vertical conductor passing through a silicon substrate, has many promising benefits to improve integration density, shorten interconnect length, and reduce power consumption. [4][5][6] However, as the operating frequency is continuously increased, the limitations of high-speed data transmission and degradation of channel bandwidth, which are induced by the inherent frequency-dependent loss of silicon substrate and electromagnetic interference, become inevitable.…”

“…As a potential candidate to meet high performance and miniaturization of next‐generation electronics, three‐dimensional integrated circuits (3D ICs) have attracted intense interests of research in recent years 1‐3 . Through‐silicon via (TSV), a vertical conductor passing through a silicon substrate, has many promising benefits to improve integration density, shorten interconnect length, and reduce power consumption 4‐6 .…”