A Review of Recent Research on Heat Transfer in Three-Dimensional Integrated Circuits (3-D ICs)

Salvi, Swapnil S.; Jain, Ankur

doi:10.1109/tcpmt.2021.3064030

Cited by 61 publications

(13 citation statements)

References 200 publications

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“…In a 3D-IC chip stack, where one end is typically allocated for electrical interconnections, only a singular end can be utilized for effective heat dissipation. Consequently, the options for heat dissipation may be constrained, particularly within the middle section of the stack [45]. Thermal management is a critical aspect of 3D ICs that has a significant impact on their performance and reliability.…”

Section: Thermal Managementmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs.

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Section: Thermal Managementmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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“…The application of a stacked three-dimensional integrated circuit(3D-IC) has offered significant improvements in the system integration and packaging density, but the overheated hot spot problem remains a key issue in chip manufacturing and operation [1,2]. The technology of 3D-IC based on through-silicon vias (TSVs) can effectively and quickly facilitate heat transfer and reduce the power consumption of chips [3].…”

Section: Introductionmentioning

confidence: 99%

Optimized method for thermal through silicon via placement with non-uniform heat sources in 3-D-IC

Ding

Zhang

2023

THERM SCI

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In the past few years, thermal through silicon via (TTSV) has been experimentally investigated as an effective heat dissipation path. Although a lot of heat dissipation-related issues have been solved in three-dimensional integrated circuit (3D-IC), there are neglections in TTSV placement with non-uniform heat sources so far. In this study, a unique optimization is proposed to locate TTSV while effectively alleviating hot spots in 3D-IC. The thermal dissipation of non-uniform heat sources are studied using the finite element method. The simulation results show that the minimum temperature is reduced by 2.1% compared with peak temperature in the single-layer chip, and by 1.9% in the three-layer chip.

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“…However, chips with high integration density dissipate high power, which consequently induces overheating problems that can cause disastrous thermal peaks. Thus, an appropriate management of thermal dynamics including thermal monitoring is required to avoid performance degradation and lifetime reduction of ICs [ 2 , 3 , 4 ]. On-chip thermal behavior can be obtained by adopting an on-chip distributed oscillator network [ 5 , 6 ], where the frequency variations generated by the integrated oscillators indicate the thermal changes in the chip.…”

Section: Introductionmentioning

confidence: 99%

Towards Real-Time Monitoring of Thermal Peaks in Systems-on-Chip (SoC)

Oukaira

Hassan

Ali

et al. 2022

Sensors

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This paper presents a method to monitor the thermal peaks that are major concerns when designing Integrated Circuits (ICs) in various advanced technologies. The method aims at detecting the thermal peak in Systems on Chip (SoC) using arrays of oscillators distributed over the area of the chip. Measured frequencies are mapped to local temperatures that are used to produce a chip thermal mapping. Then, an indication of the local temperature of a single heat source is obtained in real-time using the Gradient Direction Sensor (GDS) technique. The proposed technique does not require external sensors, and it provides a real-time monitoring of thermal peaks. This work is performed with Field-Programmable Gate Array (FPGA), which acts as a System-on-Chip, and the detected heat source is validated with a thermal camera. A maximum error of 0.3 °C is reported between thermal camera and FPGA measurements.

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A Review of Recent Research on Heat Transfer in Three-Dimensional Integrated Circuits (3-D ICs)

Cited by 61 publications

References 200 publications

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Optimized method for thermal through silicon via placement with non-uniform heat sources in 3-D-IC

Towards Real-Time Monitoring of Thermal Peaks in Systems-on-Chip (SoC)

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