RESURF n-LDMOS Transistor for Advanced Integrated Circuits in 4H-SiC

WeiBe, J.; Matthus, Christian D.; Schlichting, Holger; Mitlehner, H.; Erlbacher, Tobias

doi:10.1109/ted.2020.3002730

Cited by 25 publications

(11 citation statements)

References 24 publications

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“…Compared with the silicon-based power integrated circuits, SiC power integrated circuits can provide much higher power ratings and operate in much higher temperature applications due to their material properties [17][18][19]. It is worth mentioning that SiC lateral double-diffused metal oxide semiconductor (LDMOS) FETs are extremely important and commonly used in SiC power integrated circuits because they have excellent electrical properties and are adapted for integration with low-voltage devices [20][21][22][23]. In recent years, a lot of research has been conducted on SiC LDMOS devices, and SiC LDMOS power transistors with reduced surface field (RESURF) and field-plate (FP) technologies have been developed to optimize the trade-off relationship between the breakdown voltage (BV) and the specific on-state resistance [5,21,[24][25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

“…It is worth mentioning that SiC lateral double-diffused metal oxide semiconductor (LDMOS) FETs are extremely important and commonly used in SiC power integrated circuits because they have excellent electrical properties and are adapted for integration with low-voltage devices [20][21][22][23]. In recent years, a lot of research has been conducted on SiC LDMOS devices, and SiC LDMOS power transistors with reduced surface field (RESURF) and field-plate (FP) technologies have been developed to optimize the trade-off relationship between the breakdown voltage (BV) and the specific on-state resistance [5,21,[24][25][26][27][28]. However, the trade-off between BV and the specific on-resistance (R on,sp ) is still serious and requires alleviation.…”

Section: Introductionmentioning

confidence: 99%

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A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

Kong¹,

Duan²,

Gao³

et al. 2022

Semicond. Sci. Technol.

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A novel optimum variation lateral doping 4H-SiC lateral double-diffused metal-oxide- semiconductor field-effect transistor (LDMOS) with improved performance is proposed and numerical simulation investigated in this article. As for the proposed 4H-SiC LDMOS, an optimized three-stage variation of lateral doping (VLD) p-top layer is employed in the drift region, thus the doping concentration of the n-drift region can be significant increased, resulting an ultra-low specific resistance (Ron,sp). The breakdown voltage (BV) is also improved, since the electric field distribution of the drift region is optimized. Besides, the current saturation characteristic, gate-drain capacitance (CGD) and gate-to-drain charge (Qgd) of the proposed device are all improved, thanks to the effect of the source connected p-top region. Compared with the conventional LDMOS, the numerical simulation results show that the BV, Ron,sp and Qgd of the proposed LDMOS are improved by more than 11.9%, 47.3% and 46.3%, respectively. And the three-dimensional simulation result indicates that the entire three-stage p-top VLD layer can be performed by one-time fabrication process, which brings great convenience to future production.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

Kong¹,

Duan²,

Gao³

et al. 2022

Semicond. Sci. Technol.

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show abstract

“…The development and maturity of the SiC power device and integrated circuit technology has paved the way for the emergence and development of SiC power integrated circuits (ICs), which will empower many applications, such as automotive, industrial, energy harvesting and power conditioning [10]. In SiC power ICs, the lateral SiC power MOSFET is a crucial component, because it is easy to be integrated with the low voltage CMOS devices and other devices [11]- [13]. Recently, the SiC lateral MOSFETs with reduced surface field (RESURF) structure and field-plate structure have been proposed to improve the breakdown voltages and/or reduce the on-state resistances [5], [10], [13]- [17].…”

Section: ⅰ Introductionmentioning

confidence: 99%

“…In SiC power ICs, the lateral SiC power MOSFET is a crucial component, because it is easy to be integrated with the low voltage CMOS devices and other devices [11]- [13]. Recently, the SiC lateral MOSFETs with reduced surface field (RESURF) structure and field-plate structure have been proposed to improve the breakdown voltages and/or reduce the on-state resistances [5], [10], [13]- [17]. However, there is still a severe trade-off relationship between the specific on-resistance (Ron,sp) and the breakdown voltage (BV) in SiC lateral MOSFET.…”

Section: ⅰ Introductionmentioning

confidence: 99%

A 1200-V-Class Ultra-Low Specific On-Resistance SiC Lateral MOSFET With Double Trench Gate and VLD Technique

Kong

Gao

et al. 2022

IEEE J. Electron Devices Soc.

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An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance (Ron,sp). Numerical Simulation results show that the Ron,sp of the proposed SiC LDMOS is 3.5 mΩcm 2 with a breakdown voltage of ～1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a Ron,sp of 6.6 mΩcm 2 and a breakdown voltage of ～ 1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the Ron,sp and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.

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“…A trade-off between the V BR and the R on.sp is an essential factor in the LDMOS transistors. So, to improve this trade-off, the reduced surface field (RESURF) technology has been proposed [18,19]. To reduce the R on.sp , we can use deep gate LDMOS transistors because these structures can reduce channel resistance (R ch ) and R on.sp [20][21][22].…”

Section: Introductionmentioning

confidence: 99%

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

Gavoshani

Orouji

2021

IET Circuits, Devices & Syst

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In this study, design considerations of a new device structure are presented to improve the self-heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C-LDMOS). In this case, triple oxide trenches with an N + trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on-resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C-LDMOS.

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RESURF n-LDMOS Transistor for Advanced Integrated Circuits in 4H-SiC

Cited by 25 publications

References 24 publications

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

A 1200-V-Class Ultra-Low Specific On-Resistance SiC Lateral MOSFET With Double Trench Gate and VLD Technique

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

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