A new high-performance sidewall enhanced trench junction barrier Schottky (SET-JBS) diode is proposed in this article. In the proposed SET-JBS diode, in addition to the Schottky contact on the top anode, the sidewall of the trenches also introduces Schottky contacts, which not only increases the Schottky contact area, but also weakens the JFET (Junction Field-Effect Transistor) effect of the device, resulting in a high forward current density and a low specific on-resistance (R on,sp) with a small increase in reverse leakage current (J L). Simulation results show that the R on,sp of the proposed SET-JBS diode is reduced by 21.6% to 46.7% with less than an order of magnitude increase in leakage current compared with that of the conventional trench JBS (T-JBS) diode when the trench distance is from 2.1μm to 1.2 μm at the 2μm trench depth. And the SET-JBS diode also performs better than the trench MOS barrier Schottky (TMBS) diode when comprehensively considered the R on,sp and J L. And the figure of merit (FOM) and the trade-off relationship between the R on,sp and the breakdown voltage of the proposed SET-JBS both are better than those of the conventional T-JBS diode and TMBS diode. The forward I-V analytical model of the SET-JBS is also proposed, which is in good agreement with the simulation results. All the simulation results indicate that the proposed SET-JBS diode has promising potential in power electronics applications.
A novel optimum variation lateral doping 4H-SiC lateral double-diffused metal-oxide- semiconductor field-effect transistor (LDMOS) with improved performance is proposed and numerical simulation investigated in this article. As for the proposed 4H-SiC LDMOS, an optimized three-stage variation of lateral doping (VLD) p-top layer is employed in the drift region, thus the doping concentration of the n-drift region can be significant increased, resulting an ultra-low specific resistance (Ron,sp). The breakdown voltage (BV) is also improved, since the electric field distribution of the drift region is optimized. Besides, the current saturation characteristic, gate-drain capacitance (CGD) and gate-to-drain charge (Qgd) of the proposed device are all improved, thanks to the effect of the source connected p-top region. Compared with the conventional LDMOS, the numerical simulation results show that the BV, Ron,sp and Qgd of the proposed LDMOS are improved by more than 11.9%, 47.3% and 46.3%, respectively. And the three-dimensional simulation result indicates that the entire three-stage p-top VLD layer can be performed by one-time fabrication process, which brings great convenience to future production.
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