Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

Abstract

-A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 µm × 50 µm pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 µm × 50 µm and single readout electrode 25 µm × 100 µm 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre-and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology.

On MAPS-On-Diamond sensors and their potential as innovative devices

“…The typical area of the pixels in the readout front-end chips developed for High energy Physics application are ∼ 0.3 mm 2 or more because the need for a high spatial resolution should be balanced by the amount of circuitry that has to be implemented on the single pixel. Hence to build a hybrid pixel detector with a diamond substrate via a bump bonding procedure with the readout chip has the same limitations [14,15], i.e. is of the order of 50-55 µm.…”

RD53A: a large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades

“…Notably, the synchronous and linear FE have been included in the CHIPIX65 demonstrator chip and the differential FE in the FE65-P2 chip. Some results regarding the characterization of these prototypes can be found at [4], [5] and [6]. The synchronous FE contains a single stage Charge Sensitive Amplifier (CSA) based on a telescopic cascode scheme.…”