Reporting of standard cell placement results

Madden, Patrick H.

doi:10.1109/43.980262

Cited by 23 publications

(10 citation statements)

References 24 publications

(11 reference statements)

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“…Wire lengths listed are half-perimeter wire lengths (for the case of placement) and routed wire lengths, measured in microns (an inter-wafer is assumed here to be equivalent to one micron of wire; this value can be adjusted to match a given 3- D technology) and averaged over the 18 circuits in the benchmark. For 2-D instances, the placer is competitive with the contemporary standard-cell placers shown in [18]. With 3-D integration, we note that a 28% reduction in total wire length is achievable with just two wafers, and that 51% reduction is possible with five wafers, assuming an optimal integration technology.…”

Section: Performance Of the 3-d Standard Cell Place And Route Toolsmentioning

confidence: 68%

Design tools for 3-D integrated circuits

Das

Chandrakasan

Reif

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Abstract-We present a set of design tools for 3-D integration. Using these tools -a 3-D standard-cell placement tool, global routing tool, and layout editor -we have targeted existing standard-cell circuit netlists for fabrication using wafer bonding. We have analyzed the performance of several circuits using these tools and find that 3-D integration provides significant benefits. For example, relative to single-die placement, we observe on average 28% to 51% reduction in total wire length.

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Section: Performance Of the 3-d Standard Cell Place And Route Toolsmentioning

confidence: 68%

Design tools for 3-D integrated circuits

Das

Chandrakasan

Reif

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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“…Finally, the lack of common infrastructure makes comparison of results between different tools problematic. Both [97] and [98] discuss this particular issue in detail.…”

Section: Openaccessmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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“…For example, ACG in [28] is presented as "more suitable for interconnect plan" than existing representations, but no results on interconnect are reported. This state of confusion reminds of the critical analysis of VLSI placement literature in [15], and our work is motivated similarly. However, a major difference is that many results in floorplanning have been mathematically proven, therefore our focus is on relevance and applicability rather than correctness.…”

Section: Introductionmentioning

confidence: 99%

Are floorplan representations important in digital design?

Chan

Adya²,

Markov

2005

Proceedings of the 2005 International Symposium on Physical Design

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Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the geometry of module shapes and seeks tighter packing, as well as improvements in the asymptotic worst-case complexity of algorithms for standard tasks. In this work we consider the implications of interconnect optimization on the value of floorplan representations and establish a framework for comparing different representations. By analyzing performance bottlenecks in block packing and properties of floorplan representations, we show that many of the mathematical results in floorplanning do not translate into better VLSI layouts. This is confirmed by extensive empirical data for stand-alone floorplanners and integrated applications.

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Reporting of standard cell placement results

Cited by 23 publications

References 24 publications

Design tools for 3-D integrated circuits

Design tools for 3-D integrated circuits

Integrated logic synthesis using simulated annealing

Are floorplan representations important in digital design?

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