Are floorplan representations important in digital design?

Chan, Hayward H.; Adya, Saurabh; Markov, Igor L.

doi:10.1145/1055137.1055164

Cited by 32 publications

(31 citation statements)

References 25 publications

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“…For comparison, we ran Parquet twice for each benchmark: the first one is to let it run 10 times with the same time limit as ours; the second one is to let it run 10 times with a longer time limit such that the results are with the same quality as the ones in the work [15]. The results are reported in Table II.…”

Section: Resultsmentioning

confidence: 99%

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Exploring adjacency in floorplanning

Wang¹,

Zhou²

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-This paper describes a new floorplanning approach called Constrained Adjacency Graph (CAG) that helps exploring adjacency in floorplans. CAG extends the previous adjacency graph approaches by adding explicit adjacency constraints to the graph edges. After sufficient and necessary conditions of CAG are developed based on dissected floorplans, CAG is extended to handle general floorplans in order to improve area without changing the adjacency relations dramatically. These characteristics are currently utilized in a randomized greedy improvement heuristic for wire length optimization. The results show that better floorplans are found with much less running time for problems with 100 to 300 modules in comparison to a simulated annealing floorplanner based on sequence pairs.

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Section: Resultsmentioning

confidence: 99%

“…The other representation in Parquet, which is B * -tree, generates similar results according to the work [15] and thus is not compared here.…”

Section: B Experimental Setupmentioning

confidence: 95%

Exploring adjacency in floorplanning

Wang¹,

Zhou²

2009

2009 Asia and South Pacific Design Automation Conference

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“…They all cannot obtain desirable floorplans for the flip-chip design directly.) We shall also note that the B*-tree floorplanner is considered a leading tool in block floorplanning [6,10,20].…”

Section: Resultsmentioning

confidence: 99%

“…However, traditional floorplanning/placement algorithms do not scale well as the circuit size, complexity, and constraints increase. The B*-tree, in contrast, has been shown an efficient and effective data structure for floorplanning [6,9,20]. (In particular, the B*-tree tool is available on-line [4].)…”

Section: B Previous Workmentioning

confidence: 99%

Simultaneous block and I/O buffer floorplanning for flip-chip design

Peng

Chang

Wang

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as well as the delay skew of the paths are simultaneously minimized. We then present a hierarchical method to solve the problem. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the alternating and interacting global optimization step and the partitioning step. The global optimization step places blocks based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the blocks are divided into two groups and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of blocks, defined by the ratio of the total block area to the chip area. At last, we refine the floorplan by perturbing blocks inside a subregion as well as in different subregions. Compared with the B*-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies.

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“…Therefore, we propose an AFF technique to speed up the whole framework. Typically, fixed-outline floorplanning spends most time in computing the wirelength, as also observed in [21]. Furthermore, many floorplanning results might not be feasible because the resulting floorplans cannot fit into the bounding box.…”

Section: ) Accelerative Fixed-outline Floorplanning (Aff)mentioning

confidence: 99%

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning

Chen

Chang

Lin³

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present in this paper a new interconnect-driven multilevel floorplanner, called interconnect-driven multilevelfloorplanning framework (IMF), to handle large-scale buildingmodule designs. Unlike the traditional multilevel framework that adopts the "Λ-shaped" framework (inaccurately called the "V-cycle" framework in the literature): bottom-up coarsening followed by top-down uncoarsening, the IMF, in contrast, works in the "V-shaped" manner: top-down uncoarsening (partitioning) followed by bottom-up coarsening (merging). The top-down partitioning stage iteratively partitions the floorplan region based on min-cut bipartitioning with exact net-weight modeling to reduce the number of global interconnections and, thus, the total wirelength. Then, the bottom-up merging stage iteratively applies fixed-outline floorplanning using simulated annealing for all regions and merges two neighboring regions recursively. Experimental results show that the IMF obtains the best published fixed-outline floorplanning results with the smallest average wirelength for the Microelectronics Center of North Carolina/ Gigascale Systems Research Center benchmarks. In particular, IMF scales very well as the circuit size increases. The V-shaped multilevel framework outperforms the Λ-shaped one in the optimization of global circuit effects, such as interconnection and crosstalk optimization, since the V-shaped framework considers the global configuration first and then processes down to local ones level by level, and thus, the global effects can be handled at earlier stages. The V-shaped multilevel framework is general and, thus, can be readily applied to other problems.

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Are floorplan representations important in digital design?

Cited by 32 publications

References 25 publications

Exploring adjacency in floorplanning

Exploring adjacency in floorplanning

Simultaneous block and I/O buffer floorplanning for flip-chip design

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning

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