Design tools for 3-D integrated circuits

Das, Shamik; Chandrakasan, Anantha P.; Reif, R.

doi:10.1145/1119772.1119783

Cited by 58 publications

(10 citation statements)

References 21 publications

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“…Several tools are implemented in the past for different physical design stages, such as 3-D standard-cell placement tool, global routing tool and layout editor, in the tool chain of 3-D integration 4 . An enormous research is in progress for 3-D IC design.…”

Section: Related Work and Motivational Backgroundmentioning

confidence: 99%

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

et al. 2019

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In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

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Section: Related Work and Motivational Backgroundmentioning

confidence: 99%

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

et al. 2019

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“…Thermal aware placement and routing algorithms for 3D ICs have been presented in a number of prior publications [6][7][8] [9]. Contactless signaling between the stacked tiers using the capacitive or inductive coupling principle has been gaining traction in the circuit design community [10][11] [12].…”

Section: Introductionmentioning

confidence: 99%

A multi-story power delivery technique for 3D integrated circuits

Jain

Kim

Keane

et al. 2008

Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design - ISLPED '08

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Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some interesting facts and design challenges. A multi-story power delivery technique that can reduce the worst case DC noise by 45% and lower the overhead power consumed in the power supply network by 65% is proposed. A test chip layout in an SOI process, showing a 5.3% area overhead, demonstrates the feasibility of the scheme.

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“…A subsequent step performs 2D placement on each tier separately; the already placed tiers can serve as a guide to subsequent tiers in order to minimize wire length. However, [15] [16] [7] already identified that this approach leads to worse results in terms of wire length. We call True 3D placer a method that is able to both measure and optimize wire length in all the axis at the same time.…”

Section: Related Workmentioning

confidence: 99%

“…Das et. al [7] [9] builded a true 3D partitioning based placement engine. It recursively cuts the placement cube performing min-cut partitioning.…”

Section: Related Workmentioning

confidence: 99%

A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits

Hentschke

Sawicki

Johann

et al.

IFIP International Federation for Information Processing

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This paper presents an algorithm for I/O pins partitioning and placement targeting 3D circuits. The method starts from a standard 2D placement of the pins around a flat rectangle and outputs a 3D representation of the circuit composed of a set of tiers and pins placed at the four sides of the resulting cube. The proposed algorithm targets a balanced distribution of the I/Os that is required both for accommodating the pins evenly as well as to serve as an starting point for cell placement algorithms that are initially guided by I/O's locations, such as analytical placers. Moreover, the I/O partitioning tries to set pins in such a way the it allows the cell placer to reach a reduced number of 3D-Vias. The method works in two phases: first the I/O partitioning considering the logic distances as weights; second, fix the I/Os and perform partitioning of the cells. The experimental results show the effectiveness of the approach on balance and number of 3D-Vias compared to simplistic methods for I/O partitioning, including traditional min-cut algorithms. Since our method contains the information of the whole circuit compressed in a small graph, it could actually improve the partitioning algorithm at the expense of more CPU time. Additional experiments demonstrated that the method could be adapted to further reduce the number of 3D-Vias if the I/O pin balance constraint can be relaxed. * On leave from UNIJUI -Universidade Reg. do Noroeste do Estado do RS -Brazil Please use the following format when citing this chapter:

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Design tools for 3-D integrated circuits

Cited by 58 publications

References 21 publications

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

A multi-story power delivery technique for 3D integrated circuits

A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits

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