A 2 W, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.
A background self-calibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic analog-to-digital converters (ADCs). Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital post-processing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described by Murmann and Boser. Simulation results are presented for a 12-bit pipelined ADC architecture, similar to that described by Murmann and Boser, using nonideal interstage residue amplifiers. With calibration, the simulations show a signal-to-noise-and-distortion-ratio performance of 72 dB and a spurious-free dynamic range performance of 112 dB, with calibration tracking time constants of approximately 8 10 5 sample periods, which is over ten times faster than that reported by Murmann and Boser at a similar performance level.
Robust high-density subthreshold SRAMs are indispensable for emerging ultra-low power applications such as implantable devices, medical instruments, and wireless sensor networks. Conventional 6T SRAMs in the subthreshold region fail to deliver the density and yield requirements due to the reduced static noise margin (SNM), poor writability, limited number of cells per bitline, and reduced bitline sensing margin. 8T and 10T SRAM cells have been proposed to improve the SNM by decoupling the SRAM cell nodes from the bitline and hence making the read mode SNM equal to the hold mode SNM [1,2]. This paper introduces various circuit techniques for designing robust high-density subthreshold SRAMs: (i) decoupled cell for read margin improvement, (ii) utilizing reverse short channel effect (RSCE) for write margin improvement, (iii) eliminating data-dependent bitline leakage to enable long bitlines, (iv) virtual ground replica scheme for improved bitline sensing margin, (v) writeback scheme for data preservation during write, and (vi) optimal gate sizing based on subthreshold logical effort. Fig. 18.5.1 shows the proposed 10T SRAM cell. When read is enabled (RWL=1), the read bitline (RBL) is conditionally discharged through pull-down transistors M7, M8, and M9 depending on 'QB'. The cell node is isolated from the bitline during read operation, retaining a hold mode SNM. The 10T SRAM cell has an SNM of 76mV at a supply voltage of 0.2V while that of a conventional 6T SRAM cell is 14mV. When read is disabled (RWL=0), node A is held to V DD making the bitline leakage flow from node A to RBL, regardless of the data stored in the SRAM cell. Write operation of the proposed cell is performed by asserting WWL while the write data are loaded onto the write bitlines (WBL, WBLB). To improve the write margin, previous techniques have applied a wordline voltage that is higher than the cell voltage to increase the drive current of the write access transistors [2]. Instead, we use the governing RSCE in the subthreshold region to improve the cell writability without introducing a separate high V DD . RSCE is observed in modern CMOS devices due to the HALO pocket implants used to compensate the V t roll-off [3]. RSCE is not a concern in conventional superthreshold designs since it does not affect the device characteristics of minimum channel length transistors. However, in the subthreshold region where DIBL is reduced and current depends exponentially on V t , RSCE causes the operating current to increase with a longer channel length, as shown in Fig. 18.5.2. For a fixed device width, minimum delay is achieved at 0.36µm in the subthreshold region, which is three times longer than the minimum channel length of 0.12µm. For equal drive current, device width can be reduced as the channel length is increased, lowering the junction capacitance, which significantly contributes to the write power consumption. Using RSCE yields further advantages such as better sub-threshold slope owing to the longer channel length and reduced impact of random dopan...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.