Expanding applications for microelectronics in large-area sensor arrays, disposable sensor tapes, timeϪtemperature smart labels, radio frequency identification tags, and roll-up displays 1Ϫ4 motivate efforts to integrate electronics onto flexible plastic, paper, or metal substrates. A principal strategy for achieving flexible electronics is to employ graphic arts methods such as flexographic or ink-jet printing to pattern metallic, semiconducting, and insulating inks onto foils and paper. 5Ϫ10 Liquid phase printing offers the potential for high-throughput roll-toroll or sheet-to-sheet processing of electronics on large-area substrates, facilitating applications where large areas are necessary (e.g., displays) and also potentially translating into low production cost. Yet the challenge for printed electronics is to achieve high-performance circuits. The inherently low carrier mobilities of many printable organic or nanoparticle-based semiconductors lead to reduced transistor switching frequencies and high circuit supply voltages. Alternative strategies in which silicon chips are bonded to flexible substrates (by transfer printing or pick-andplace methods) are also attractive because they benefit from the superior electronic properties of silicon and the very advanced state of silicon microelectronics technology.11 In a competitive environment, the success of liquid phase printed electronics depends on substantial performance improvements, in particular, the development of faster, lower power printed circuits. Figure 1a displays a summary of reported signal delay times versus supply voltages for ring oscillator circuits based on organic semiconductors and carbon nanotube (CNT) arrays. It is evident that for nonprinted organic ring oscillators (open blue symbols) signal delays of 1Ϫ10 s have been achieved but only for supply voltages of 10Ϫ100 V, 12Ϫ24 while for supply voltages in the range of 4Ϫ10 V, the delay is above 10 s for the fastest circuits, with most displaying Ͼ1 ms switching times.25Ϫ28 Reports of printed ring oscillators are less common (solid green symbols in Figure 1a), and these circuits have generally required tens of volts to achieve switching times on the order of 1 ms.29Ϫ32 Such large voltages are not practical for many potential applications of flexible electronics where power will be supplied by thin-film batteries or radio frequency fields. Very recently, unipolar, p-type electrolyte-gated ring oscillator circuits have been demonstrated that indeed operate at very low

The fabrication and characterization of printed ion‐gel‐gated poly(3‐hexylthiophene) (P3HT) transistors and integrated circuits is reported, with emphasis on demonstrating both function and performance at supply voltages below 2 V. The key to achieving fast sub‐2 V operation is an unusual gel electrolyte based on an ionic liquid and a gelating block copolymer. This gel electrolyte serves as the gate dielectric and has both a short polarization response time (<1 ms) and a large specific capacitance (>10 µF cm−2), which leads simultaneously to high output conductance (>2 mS mm−1), low threshold voltage (<1 V) and high inverter switching frequencies (1–10 kHz). Aerosol‐jet‐printed inverters, ring oscillators, NAND gates, and flip‐flop circuits are demonstrated. The five‐stage ring oscillator operates at frequencies up to 150 Hz, corresponding to a propagation delay of 0.7 ms per stage. These printed gel electrolyte gated circuits compare favorably with other reported printed circuits that often require much larger operating voltages. Materials factors influencing the performance of the devices are discussed.

A central challenge for printed electronics is to achieve high operating frequencies (short transistor switching times) at low supply biases compatible with thin film batteries. In this report, we demonstrate partially printed five-stage ring oscillators with >20 kHz operating frequencies and stage delays <5 μs at supply voltages below 3 V. The fastest ring oscillator achieved 1.2 μs delay time at 2 V supply. The inverter stages in these ring oscillators were based on ambipolar thin film transistors (TFTs) employing semiconducting, single-walled carbon nanotube (CNT) networks and a high capacitance (∼1 μF/cm(2)) ion gel electrolyte as the gate dielectric. All materials except the source and drain electrodes were aerosol jet printed. The TFTs exhibited high electron and hole mobilities (∼20 cm(2)/(V s)) and ON/OFF current ratios (up to 10(5)). Inverter switching times t were systematically characterized as a function of transistor channel length and ionic conductivity of the gel dielectric, demonstrating that both the semiconductor and the ion gel play a role in switching speed. Quantitative scaling analysis suggests that with suitable optimization low voltage, printed ion gel gated CNT inverters could operate at frequencies on the order of 1 MHz.

Abstract-Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique.

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Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

The emergence of semiconducting materials with inert or dangling bond-free surfaces has created opportunities to form van der Waals heterostructures without the constraints of traditional epitaxial growth. For example, layered two-dimensional (2D) semiconductors have been incorporated into heterostructure devices with gate-tunable electronic and optical functionalities. However, 2D materials present processing challenges that have prevented these heterostructures from being produced with sufficient scalability and/or homogeneity to enable their incorporation into large-area integrated circuits. Here, we extend the concept of van der Waals heterojunctions to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type amorphous indium gallium zinc oxide (a-IGZO) thin films that can be solution-processed or sputtered with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions exhibit antiambipolar transfer characteristics with high on/off ratios that are well-suited for electronic, optoelectronic, and telecommunication technologies.