Impact of NBTI on SRAM Read Stability and Design for Reliability

Kumar, Sanjay; Kim, Chris H.; Sapatnekar, Sachin S.

doi:10.1109/isqed.2006.73

Cited by 250 publications

(157 citation statements)

References 22 publications

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“…Although for smaller designs the use of external test equipment is most suitable for the post-manufacture stage, it is envisaged that built-in test structures may increasingly be used with the CAT technique. Additional advantages of this approach are that it provides the potential for regular test and calibration cycles, which would tackle the increasing challenge of age related variability effects [3].…”

Section: Critical Device Identificationmentioning

confidence: 99%

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Yield improvement using configurable analogue transistors

Wilson

Wilcock

2008

Electron. Lett.

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Continued process scaling has led to significant yield and reliability challenges for today's designers. Analogue circuits are particularly susceptible to poor variation, driving the need for new yield resilient techniques in this area. This paper describes a new configurable analogue transistor structure and supporting methodology that facilitates variation compensation at the post-manufacture stage. The approach has demonstrated significant yield improvements and can be applied to any analogue circuit.

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Section: Critical Device Identificationmentioning

confidence: 99%

“…significant changes in a circuit's performance over its lifetime [3]. In the case of analogue circuits the impact of variability can be complex due to a large number of performance specifications.…”

mentioning

confidence: 99%

Yield improvement using configurable analogue transistors

Wilson

Wilcock

2008

Electron. Lett.

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“…Static timing analysis (STA) techniques considering NBTI degradation were proposed [11,12]. Based on these NBTI-aware circuit performance degradation models and STA techniques, researchers have investigated design techniques that can mitigate NBTI effects, such as transistor sizing [13], adjustment of dynamic operation conditions (supply voltage (V dd ), temperature (T ), and signal probability (SP)) [11], bit-flipping technique [14]. Higher level technique, such as NBTI-aware synthesis [15] was also studied.…”

Section: Introductionmentioning

confidence: 99%

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang

Chen

Wang

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-1 As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input patterns of circuits. In this paper, we propose a co-simulation flow to study NBTI-induced circuit degradation and leakage power, taking into account the different behaviors between circuit active and standby time. Based on this flow, we evaluate the efficacy of Input Vector Control (IVC) technique on mitigating circuit aging and reducing standby leakage power with experiments on benchmark circuits that are implemented in 90nm, 65nm, and 45nm technology nodes. The IVC technique is proved to be effective to mitigate NBTI-induced circuit degradation, saving up to 56% circuit performance degradation at 65nm technology node, and on average 30% circuit performance degradation across different technology nodes. Meanwhile, IVC technique can save up to 18% of the worst case leakage power. Since leakage power and NBTI-induced circuit degradation have different dependencies on the input patterns, we propose to derive Pareto sets for designers to explore trade-offs between the life-time reliability and leakage power.

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“…They also propose to balance the degradation of the PMOS devices in SRAMbased memory structures by storing appropriate data value into the SRAM cells when they hold invalid data. Kumar et al [18] propose a similar technique to periodically flip the contents of SRAM cells to balance the wear on the PMOS transistors. The cost of such a technique comes from the extra XNOR gates required to invert/deinvert data with the invert bit (global signal indicating the current mode), which has an impact in cycle time.…”

Section: Recovery Enhancement Techniques For Nbtimentioning

confidence: 99%

“…However, due to the cross-coupled nature of the inverters, only one of the PMOS devices can be put into the recovery mode. Therefore, previously proposed recovery enhancement techniques attempt to balance the wearout of the two PMOS devices by putting each PMOS into the recovery mode 50% of the [18,17,19]. We propose a 6T SRAM cell design shown in Figure 4.2 which is capable of normal operations (read, write, and hold) as well as providing an NBTI recovery mode (when the cell does not contain valid data) that we call the recovery boost mode where both PMOS devices within the cell undergo recovery at the same time.…”

Section: Basics Of Recovery Boostingmentioning

confidence: 99%

A Multi-Level Approach to NBTI Mitigation in Processors

Siddiqua

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We are in the era of multicore processors and it is expected that the number of the processing cores on a chip will steadily increase over the next decade, driven by Moore's Law. While technology scaling has benefitted high performance, the scaling has a dark side too: a degradation in the reliability of silicon devices. Processors have become highly susceptible to a variety of reliability problems in silicon, such as particle induced soft errors and hard errors. Therefore, processors have to be designed to provide adequate protection against these reliability problems while maintaining high performance and energy efficiency. Designing a reliable computer system is a large and complex multi-dimensional and multi-level problem, comprising of different hardware blocks, reliability phenomena, design layers, metrics, and optimization techniques. This dissertation considers a key emerging reliability phenomenon: Negative Bias Temperature Instability (NBTI). This dissertation develops NBTI mitigation techniques for the logic and memory structures in the processor that impose very little performance, power, and area overheads. This research also creates the foundation for understanding NBTI in the context of one other important processor reliability problem: process variations.

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Impact of NBTI on SRAM Read Stability and Design for Reliability

Cited by 250 publications

References 22 publications

Yield improvement using configurable analogue transistors

Yield improvement using configurable analogue transistors

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

A Multi-Level Approach to NBTI Mitigation in Processors

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