On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang, Yu; Chen, Xiaoming; Wang, Wenping; Balakrishnan, Varsha; Cao, Yu; Xie, Yuan; Yang, Huazhong

doi:10.1109/isqed.2009.4810264

Cited by 58 publications

(25 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this paper, we implemented the traditional IVC method which was proposed in [22]. The optimal input vector of IVC is obtained from 2000 input vectors which are generated randomly.…”

Section: Co-optimization Resultsmentioning

confidence: 99%

See 1 more Smart Citation

M-IVC: Applying multiple input vectors to co-optimize aging and leakage

Song

Han

2012

Microelectronics Journal

View full text Add to dashboard Cite

“…In this paper, we implemented the traditional IVC method which was proposed in [22]. The optimal input vector of IVC is obtained from 2000 input vectors which are generated randomly.…”

Section: Co-optimization Resultsmentioning

confidence: 99%

“…In [5], Wang et al explored the possibility that using the minimum leakage vector (MLV) to reduce NBTI-induced delay degradation. In the followed work [22], they evaluated the effectiveness of IVC on simultaneously reducing circuit aging and leakage at different processes.…”

Section: Introductionmentioning

confidence: 99%

M-IVC: Applying multiple input vectors to co-optimize aging and leakage

Song

Han

2012

Microelectronics Journal

View full text Add to dashboard Cite

“…However, the impacts of the input vector on delay degradation and leakage power are not in a same direction; the optimal input vector for minimizing the postaging delay may not be the best one to minimize the leakage power and vice versa. Wang et al proposed a probability-based (PB) method to find the best input vector that has the minimum NBTI effect and/or leakage for the circuit [33]. However, the PB method is based on heuristic and random simulations, so the computation cost is high and the result may not be the optimal.…”

Section: Minimum Nbti Vector Selection Considering Power Effectmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

View full text Add to dashboard Cite

As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for Very Large Scale Integration (VLSI) circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for complementary metal oxide semiconductor (CMOS) devices. Because both the NBTI and leakage are dependent on the input vector of the circuit, we present an input vector control (IVC) method based on a linear programming algorithm, which can co-optimize circuit aging and power dissipation simultaneously. In addition, our proposed IVC method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed combination method.

show abstract

“…Other proposed ideas include online test techniques for failure analysis, introspective sensor-based methods for reduced aging, and intelligent power gating. Finally, circuits may be sent to sleep states that are designed to minimize BTI degradation through input vector control [22]: however, the gains of such methods are relatively small.…”

Section: Circuit Optimizationmentioning

confidence: 99%

What happens when circuits grow old: Aging issues in CMOS design

Sapatnekar¹

2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

View full text Add to dashboard Cite

As CMOS technologies have shrunk to tens of nanometers, aging problems have emerged as a major challenge. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to analyze and optimize the reliability of larger circuits. This talk will provide an introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, examining solutions that could practically be applied to analyze or improve the lifetime of a design while maintaining consistency to accurate device-level models and the associated physics.CIRCUIT-LEVEL ANALYSIS OF AGING Aging effects are described by the classical bathtub curve: after a steep initial failure rate, the failures level off for a while before rising again, resulting in a bathtub-like shape for the number of failures as a function of time. Aging is strongly sensitivity to process parameter variations, as well as to onchip temperature and supply voltage level changes. Here, we overview analysis methods for prominent aging mechanisms, based on both conventional and newer physical models. Bias temperature instability (BTI) is a device aging phenomenon that causes threshold voltage shifts over long periods of time in the presence of voltage stress at the gate, eventually causing the circuit to fail to meet its specifications. A PMOS transistor in an inverter experiences negative BTI stress when its gate node is at logic 0, and the resulting increase in the threshold voltage is partially reversed when the voltage stress is removed (i.e., a logic 1 is applied). A similar phenomenon of positive BTI affects the threshold voltage of NMOS devices when they are stressed, and relaxes the degradation on the removal of stress. The magnitude of degradation depends on the ratio of the stressed time to unstressed time, i.e., the signal probability (SP) of the gate input. There are two widely-used theories for BTI. The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade. Neither theory fully explains experimental observations, and it has been posited that R-D and CT mechanisms coexist. The CT model predicts high variability in small devices, making variability a major factor for memories. For logic circuits, however, large transistors and averaging effects on critical paths significantly mitigate variability [4]. Hot carrier injection (HCI) in MOSFETs is caused by the acceleration of carriers (electrons/holes) under lateral electric fields in th...

show abstract

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Cited by 58 publications

References 26 publications

M-IVC: Applying multiple input vectors to co-optimize aging and leakage

M-IVC: Applying multiple input vectors to co-optimize aging and leakage

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

What happens when circuits grow old: Aging issues in CMOS design

Contact Info

Product

Resources

About