Replacement metal gate extendible to 11 nm technology

Yoshida, N.; Fu, Xinyu; Xu, Kun; Lei, Yu; Yang, Hui; Sun, Shiyu; Chen, Hao; Darlak, Andrew; Donohoe, Ray; Lazik, C.; Jakkaraju, R.; Noori, Atif; Hung, Steven; Peidous, Igor V.; Chang, Chorng‐Ping; Brand, A.

doi:10.1109/vlsit.2012.6242471

Cited by 7 publications

(6 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In RMG-HKL, after dummy-dielectric removal with diluted-HF or siconi clean, 14,16) oxidation in O 3 is used for the IL-SiO 2 formation prior to the high-k dielectric deposition. Figure 2 shows schematics of the RMG-HKL stacks evaluated in this work for n-EWF engineering, all with similarly grown IL-SiO 2 / HfO 2 and using W 13,14) or Al 14,[17][18][19] as fill-metal. RF-PVD deposition processes, used for TiN and/or TiAl layers formation, are run at room temperature (RT), while layers obtained by ALD for EWF engineering are grown at higher temperatures, of up to 550 C. W is deposited by the sequence: ALD (300 C) !…”

Section: Rmg Modulementioning

confidence: 99%

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

Veloso

Chew

Higuchi

et al. 2013

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (V T) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (J G). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-V T: 1) conformal, lower-J G ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

show abstract

Section: Rmg Modulementioning

confidence: 99%

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

Veloso

Chew

Higuchi

et al. 2013

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…Alternatively, as described in Ref. 21, an ALD-TiN/ALD-TaN bilayer with Co x Al y fill-metal 19,21,[29][30][31][32][33] is used for gate metallization, wherein Al is deposited using a high-productivity physical vapor deposition technique (HP-PVD), with a low temperature (400 °C) reflow, and in combination with a CVD-Co wetting layer. ALD layers for EWF engineering are grown at temperatures ¯550 °C.…”

Section: Device Fabricationmentioning

confidence: 99%

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

Veloso

Boccardi

Ragnarsson

et al. 2014

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (J G) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (N it) down to narrower fin devices [fin width (W Fin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |V T|, and substantially improved reliability behavior due to reduction of bulk defects.

show abstract

“…With high aspect ratio and CD scaling of the trench, however, aluminum trench gap fill has become one of the most critical challenges in the gate-last approach. This paper presents a novel wetting layer solution to this gap-fill issue [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Aluminum Gap Fill Challenge and Evolution for Metal Gate

Wu¹,

Luo²,

He³

et al. 2014

ECS Trans.

View full text Add to dashboard Cite

High-κ metal gates have become the new paradigm in volume production of high-performance logic devices since the 45nm node. At the same time, aluminum is used for gap fill in the metal gate trench. As the technology node shrinks from 32/28nm to less than 20nm, the gate CD (critical dimension) has become smaller and aluminum gap fill has become the big process integration challenge. This paper addresses the aluminum gap fill challenge and extendibility solutions.

show abstract

Replacement metal gate extendible to 11 nm technology

Cited by 7 publications

References 0 publications

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

Aluminum Gap Fill Challenge and Evolution for Metal Gate

Contact Info

Product

Resources

About