Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST

Ahmed, Fahad; Milor, Linda

doi:10.1109/vts.2010.5469614

Cited by 42 publications

(23 citation statements)

References 9 publications

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“…However, a threshold can be found when the number of traps links directly to circuit-level failure, as was demonstrated in [2].…”

Section: ) Bias Temperature Instability (Bti)mentioning

confidence: 93%

“…Since r is the fraction of the total possible recovery remaining, equation (2) can now be used to divide the total degradation during stress from (2) into a recoverable component and a permanent component [19] with the recoverable component given by:…”

Section: ) Bias Temperature Instability (Bti)mentioning

confidence: 99%

“…where κ is the total density of traps available for generation, a E is the activation energy, k is the Boltzmann's constant, 2 κ is a device constant dependent on the field acceleration factor, and 0 E is the oxide electric field. Traps form throughout the oxide, and when the number of traps exceeds a threshold, a leakage path forms through the oxide.…”

Section: ) Bias Temperature Instability (Bti)mentioning

confidence: 99%

“…Post-silicon reliability is still heavily dependent on reactive measures, such as error detection and error correction. The use of on-chip sensors [2], complemented by post-silicon tuning [3], is also steadily increasing with the aim of extending system lifetime. However, since they do not mitigate the aging process itself, the effectiveness of such measures is always constrained due to the following reasons.…”

Section: Introductionmentioning

confidence: 99%

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Wearout-aware compiler-directed register assignment for embedded systems

Ahmed

Sabry

Atienza

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.

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“…However, a threshold can be found when the number of traps links directly to circuit-level failure, as was demonstrated in [2].…”

Section: ) Bias Temperature Instability (Bti)mentioning

confidence: 93%

Section: ) Bias Temperature Instability (Bti)mentioning

confidence: 99%

Section: ) Bias Temperature Instability (Bti)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Wearout-aware compiler-directed register assignment for embedded systems

Ahmed

Sabry

Atienza

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

Self Cite

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“…In order to evaluate the time zero variation and aging status (V T value) of the SRAM cells in a cache memory array, an on chip monitoring circuit is required [16,17,18]. In this work, we propose a monitoring approach that can measure the BTI wearout of the individual SRAM memory cells in each memory column, which also considers the process variation among the SRAM cells.…”

Section: Aging Monitor In Sram Cellsmentioning

confidence: 99%

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Pouyan

Amat

Barajas

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.

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