Reliability study of thin inter-poly dielectrics for non-volatile memory application

Mori, S.; Kaneko, Yukio; Arai, Norihisa; Ohshima, Y.; Araki, Hirohiko; Narita, Kazuo; Sakagami, E.; Yoshikawa, K.

doi:10.1109/relphy.1990.66076

Cited by 20 publications

(8 citation statements)

References 8 publications

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“…The high thermal budget is suspected of deteriorating the surface roughness of FG and producing an inferior IPD quality due to phosphorus diffusion. 6 Thus, rf plasma nitridation at room temperature without PNA shows lower gate leakage current. In considering both the programming speed and the current leakage in rf plasma nitridation modes, it is the trade-off between adding PNA and skipping the PNA step.…”

Section: Resultsmentioning

confidence: 99%

“…To achieve a high control gate coupling ratio ͑GCR͒ without sacrificing IPD capabilities, the critical thickness of the IPD stack films should be further reduced to maintain the GCR during dimension shrinkage. 5,6 However, the current leaking through the IPD film has been found to be the primary factor that limits reliability. [7][8][9] To reduce the leakage current or direct tunneling current, a small equivalent oxide thickness ͑EOT͒ with a higher dielectric constant value is required to enhance the GCR and programming speed and to address the reliability problems.…”

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confidence: 99%

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Study of Retention Characteristics and Program Speed Enhancement Using Plasma Nitridation on Interpoly Dielectric

Lien

2010

J. Electrochem. Soc.

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The interpoly dielectric ͑SiO 2 -SiN-SiO 2 ͒ in floating gate NAND flash memory, as it is used to bolster both programming speed and data retention, has been extensively investigated in studies examining plasma nitridation technologies. The bird's beak, as found on an interpoly dielectric edge, likely contributes to a degradation program/erase performance and reliability in cell operation and is abnormally increased above 12 Å during gate sidewall oxidation. This phenomenon can be effectively reduced to less than 1.5 Å through the application of nitrogen plasma nitridation on the floating gate and on the top oxide of the interpoly dielectric. In terms of control gate coupling capability and program voltage, both the physical and electrical properties of the interpoly dielectric can improve by 6% and 1.2 V, respectively. Nevertheless, this study found that data retention problems resulting from plasma nitridation, a process which induces the oxynitride remaining in shallow trench isolation, are the source of electron leakage through the word line. To reduce charging loss and sustain the coupling capabilities of the control gate, selective oxynitride removal with diluted HF is proposed. This interpoly dielectric can enhance memory characteristics and also extends the functional limitation of the NAND flash memory to the 40 nm generation.Nonvolatile memories have been growing rapidly in recent years due to the increasing demands of portable and embedded devices. Among them, floating gate ͑FG͒ NAND flash is a sequential access device used for mass storage applications. It achieves a higher density at a lower cost per bit, making it ideal for MP3 players and digital cameras as well as applications requiring mass storage of data. However, as the devices have become smaller, problems with the process and the fundamental physical limitations of the FG NAND flash memory cells have risen. First, the abnormal increase in gate oxide and interpoly dielectric ͑IPD͒ thickness degrades the intrinsic oxide reliability during thermal oxidation processes. 1,2 To address these problems, nitrogen was introduced on the polydielectric interface to eliminate gate oxide and IPD deterioration. However, a precise nitrogen profile is difficult to control using a conventional rapid thermal process ͑RTP͒, which may induce device failure. 3,4 Second, in the past decade, the IPD film has become a critical process in the dimensions of an aggressive device. To achieve a high control gate coupling ratio ͑GCR͒ without sacrificing IPD capabilities, the critical thickness of the IPD stack films should be further reduced to maintain the GCR during dimension shrinkage. 5,6 However, the current leaking through the IPD film has been found to be the primary factor that limits reliability. 7-9 To reduce the leakage current or direct tunneling current, a small equivalent oxide thickness ͑EOT͒ with a higher dielectric constant value is required to enhance the GCR and programming speed and to address the reliability problems.The introduction of stronger Si-N ...

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

Study of Retention Characteristics and Program Speed Enhancement Using Plasma Nitridation on Interpoly Dielectric

Lien

2010

J. Electrochem. Soc.

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“…Saat terjadi miniaturisasi perangkat, ketebalan oksida akan berkurang dan membuatnya rentan terhadap degradasi yang disebabkan oleh tingginya medan listrik yang umumnya digunakan dalam proses penghapusan flash memory. Degradasi ini dapat menyebabkan arus bocor, yang dapat menimbulkan sejumlah masalah pada perangkat memori seperti gangguan proses pembacaan [9], proses pemrograman /penghapusan yang lebih lambat, serta retensi data yang buruk [10]. Menurut Mozzami dan Hu [11], arus bocor berasal dari proses terobosan disertai perangkap muatan dimana kerapatan perangkap yang dihasilkan dalam oksida meningkat seiring dengan bertambahnya medan listrik dan penurunan ketebalan oksida.…”

Section: Latar Belakangunclassified

Studi Elektrostatik Elektroda Runcing dan Aplikasinya pada Perangkat Floating Gate Memory

2021

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Pada penelitian ini, potensial elektrostatik dari struktur floating gate runcing dalam sel memori split gate dipelajari secara analitik dan numerik. Penelitian ini bertujuan memberikan pendekatan sederhana untuk mempelajari diagram pita energi pada perangkat memori. Diagram energi yang dihasilkan dapat digunakan untuk mempelajari transmitansi elektron dan rapat arus terobosan. Pada studi ini, floating gate runcing dimodelkan sebagai elektroda berbentuk segitiga. Profil potensial elektrostatik elektroda segitiga ini dihitung secara analitik dengan menyelesaikan nilai batas dari persamaan Laplace dalam koordinat polar. Profil potensial dari perhitungan analitik ini lalu dibandingkan dengan profil potensial dari simulasi numerik. Dari hasil perhitungan diperoleh bahwa profil diagram energi yang dihitung secara analitik cukup sesuai dengan yang diperoleh dari simulasi numerik. Adapun terdapat sedikit perbedaan antara profil diagram pita analitik dan numerik dikarenakan elektroda segitiga diasumsikan terbuat dari logam sehingga pembentukan sumur kuantum pada permukaan floating gate diabaikan. Dari hasil permodelan analitik diperoleh bahwa sumur kuantum yang terbentuk pada tegangan sekitar 10 V (sesuai dengan tegangan hapus perangkat memori flash) adalah cukup dangkal, sehingga profil potensial yang terbentuk menjadi sangat mendekati hasil simulasi numerik. Dari hasil perhitungan diperoleh pula bahwa rapat arus terobosan yang dihitung menggunakan model kami memberikan hasil yang sangat dekat dengan hasil perhitungan dari model injektor silinder yang digunakan oleh peneliti dari Silicon Storage Technology (SST) sebagai produsen produk flash memory dengan floating gate berbentuk runcing.

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“…Like other floating gate devices, EPROM is vulnerable to gate charge leakage which can eventually result in programming data loss [6].…”

Section: Introductionmentioning

confidence: 99%

Analysis and reliability test to improve the data retention performance of EPROM circuits

Luan

DiVita

2013

International Symposium on Quality Electronic Design (ISQED)

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Data retention Iifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed-a single transistor EPROM cell as weil as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention Iifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.

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Reliability study of thin inter-poly dielectrics for non-volatile memory application

Cited by 20 publications

References 8 publications

Study of Retention Characteristics and Program Speed Enhancement Using Plasma Nitridation on Interpoly Dielectric

Study of Retention Characteristics and Program Speed Enhancement Using Plasma Nitridation on Interpoly Dielectric

Studi Elektrostatik Elektroda Runcing dan Aplikasinya pada Perangkat Floating Gate Memory

Analysis and reliability test to improve the data retention performance of EPROM circuits

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