Plastic-encapsulated packages are known to suffer package stress issues which often cause undesired shifts in the IC electrical parameters. Two types of package stress are analyzed and their contributions to the overall package stress in a Quad-Flat No-leads (QFN) Package are experimentally studied in this paper. The volumetric package stress generated by the mold compound is analyzed using the material properties of the bulk modulus and the volumetric coefficient of thermal expansion (vCTE). The in-plane package stress generated by the die and the die-attach material is analyzed using the structural analysis method with the introduction of an improved Suhir solution to evaluate the in-plane normal stress at the active area of the IC die. These theoretical analysis results are further experimentally studied with the functional measurements on a precision CMOS bandgap voltage reference in a QFN package. Using the combination of two different die-attach methods and two different die-coating conditions, the parametric variations in the bandgap voltage can be correlated with the different types of package stress. The actual test data presented in this paper are in good agreement with the theoretical analysis results.Index Terms-In-plane package stress, microelectronics packaging, package stress, structural analysis method, volumetric package stress.
We present materials development in fabricating thin film devices for the conversion of wind energy as a sustainable energy source. We demonstrate the feasibility of piezoelectric polymer thin film devices to harvest wind energy in a miniature wind tunnel. Using an example of prototype device based on polyvinylidene fluoride (PVDF) thin film devices, we are able to obtain electrical power from the wind’s energy through the mechanical deformation of PVDF, such as that obtained from the films flapping in the wind. We have obtained a preliminary result of 1 mW power (at 15 mph wind) with a single layer of PVDF of 4 x 2 inches and 50 μm in thickness sandwiched between two thin gold electrode films. Additionally, the fracturing of metallic electrodes over time from the induced strain of this application lead to the significance of examining carbon nanotubes as compliant electrodes offering better mechanical properties while maintaining necessary electrical properties.
Data retention Iifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed-a single transistor EPROM cell as weil as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention Iifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.
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