Relaxed decimation filter specifications for wireless transceivers

Grati, Khaled; Ghazel, Adel; Naviner, Lírida Alves de Barros

doi:10.1109/icecs.2002.1046228

Cited by 4 publications

(3 citation statements)

References 4 publications

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“…The ASIC core measurement calculated as 0.308×0.308 mm2 on 0.18 µm Silterra and 1.148×1.148 mm2 on 0.35 µm MIMOS technology library. The results prove high enlargement of CIC filter performance in trade-off between power and speed compare to the previous similar research work (Shahana et al, 2007;Sun and Chen, 2008;Mortazavi et al, 2009;Brandt and Wooley, 1994;Djadi et al, 1994;Ciletti, 2003;Grati et al, 2002).…”

Section: Discussionsupporting

confidence: 79%

“…The dynamic range of proposed CIC filter is 98 dB which satisfies wireless communication transceiver systems (Grati et al, 2002).…”

Section: Resultsmentioning

confidence: 91%

“…As shown in Table 2, the synthesis report of Xilinx ISE environment indicates the maximum throughput of 330 MHz in filter specification. The dynamic range of proposed CIC filter is 98 dB which satisfies wireless communication transceiver systems (Grati et al, 2002). To optimize the projected CIC filter in terms of power consumption and active core area measurement ASIC implementation was performed successfully.…”

Section: Resultsmentioning

confidence: 99%

See 2 more Smart Citations

VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

Teymourzadeh¹,

Algnabi²,

Othman³

et al. 2010

American J. of Engineering and Applied Sciences

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Problem statement:The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm 2 . Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

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