Abstract:Problem statement:The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. Approach: This research presented the design of the novel class of decimation an… Show more
“…From the experimental results, it has been noted that the selected parameters is needed to further apply with other speech technology. For examples, the parameters are expected to be applied in the tree-based context clustering in Thai speech synthesis (Chomphan and Kobayashi, 2007;Hassini et al, 2009;Jenq et al, 2009;Teymourzadeh et al, 2010) to categorize the speech units into tone groups. The data sharing in each of the speech unit clusters can consequently improve the efficiency of the overall synthesis system.…”
Problem statement: In tonal language speech; such as Thai, Mandarin and Vietnam, tone is
an important feature of a syllable that must be taken into consideration, since tone is a supra-segmental
feature in the speech prosody. Modeling of tone with high accuracy could enhance the quality of
synthesized speech in the speech synthesis system. This study focuses on a model analysis of
fundamental frequency (F0) contours of Thai tones using tone-geometrical model. Approach: Tonegeometrical
model applied is this study is a basic model which is expected to extract the dimensional
features of a syllable-length portion of fundamental frequency contour. Seven selected parameters are
extracted from a syllable-length portion of fundamental frequency contour and then are analyzed.
Results: In the experiments, 2,500 speech utterances from TSynC-1 speech database were selected and
used as speech materials. The distributions for all seven parameters are presented. The statistical
figures of mean and standard deviation values from five tones are also calculated. The results show
that most of the proposed parameters can distinguish five Thai tones explicitly. Conclusion: From the
finding, the proposed parameters of tone-geometrical model could be further applied in the speech or
other speech processing technologies
“…From the experimental results, it has been noted that the selected parameters is needed to further apply with other speech technology. For examples, the parameters are expected to be applied in the tree-based context clustering in Thai speech synthesis (Chomphan and Kobayashi, 2007;Hassini et al, 2009;Jenq et al, 2009;Teymourzadeh et al, 2010) to categorize the speech units into tone groups. The data sharing in each of the speech unit clusters can consequently improve the efficiency of the overall synthesis system.…”
Problem statement: In tonal language speech; such as Thai, Mandarin and Vietnam, tone is
an important feature of a syllable that must be taken into consideration, since tone is a supra-segmental
feature in the speech prosody. Modeling of tone with high accuracy could enhance the quality of
synthesized speech in the speech synthesis system. This study focuses on a model analysis of
fundamental frequency (F0) contours of Thai tones using tone-geometrical model. Approach: Tonegeometrical
model applied is this study is a basic model which is expected to extract the dimensional
features of a syllable-length portion of fundamental frequency contour. Seven selected parameters are
extracted from a syllable-length portion of fundamental frequency contour and then are analyzed.
Results: In the experiments, 2,500 speech utterances from TSynC-1 speech database were selected and
used as speech materials. The distributions for all seven parameters are presented. The statistical
figures of mean and standard deviation values from five tones are also calculated. The results show
that most of the proposed parameters can distinguish five Thai tones explicitly. Conclusion: From the
finding, the proposed parameters of tone-geometrical model could be further applied in the speech or
other speech processing technologies
“…Such a venture would produce a blueprint or conceptual map similar to blueprints of construction projects. Additional study can pursue application of the FM-based methodology to technical issues in VLSI design (Teymourzadeh et al, 2010), other engineering descriptions (Azadeh and Ghaderi, 2006;Verma et al, 2009;Haddad, 2009) and management (Papadamou and Stephanides, 2004;Ismail et al, 2010). …”
Problem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based) lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as control flow and data structure. It was important to fill the gap between these two levels of description because VLSI chip manufacturing was a complex management project and providing a conceptual detailed depiction of the design process would assist in managing operations on the great number of generated artifacts. Approach: This study introduces a conceptual framework representing flows and transformations of various descriptions (e.g., circuits, technical sketches) to be used as a tracking apparatus for directing traffic during the VLSI design process. The proposed methodology views a description as an integral element of a process, called a flow system, constructed from six generic operations and designed to "handle" descriptions. It draws maps of flows of representations (called flowthings) that run through the design flow. These flowthings are created, transformed (processed), transferred, released and received by various functions along the design flow at different levels (a hierarchy). The resultant conceptual framework can be used to support designers with computer-aided tools to organize and manage chains of tasks. Results: The proposed model for managing the VLSI design process was characterized by being conceptual (no technical or implementation details) and can be uniformly applied at different levels of design and to various kinds of artifacts. The methodology is applied to describe the VLSI physical design stage that includes partitioning, floorplanning and placement, routing, compaction and extraction and verification. Conclusion: The resultant conceptual picture demonstrates a viable description method that can be adapted for different stages and used in developing systems for managing the VLSI design process.
“…Field Programmable Gate Arrays (FPGAs) are good choice for hardware realization but with limitations in design optimization. Furthermore, FPGA implementation is good for prototyping where, the aim is to predict the behavior of design in real world applications, there are many DSP systems reported in literature few of them are (Palaniappan and Zulkifli, 2007;Benhamid and Othman, 2009;Rais et al, 2010;Rais, 2010;Teymourzadeh et al, 2010). Application Specific Integrated Circuits (ASIC) is the most feasible technology to realize DSP algorithms and any other complex algorithm, without much limitations in optimizing the design.…”
The orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used in Digital Signal Processing (DSP). Today's DSP applications require fast processing time in order to meet the challenges of the real time systems. State-of-the-art implementation technologies are therefore being used. This study describes the design and implementation of Rademacher and Walsh functions targeted to the state-of-the-art Cell Based Integrated Circuits (CBIC) technology. High level design techniques are used with the help of advanced EDA tools from SYNOPSYS International. Optimized VHDL models have been developed and used for design entry. The design is thoroughly verified using advanced verifications tools. The design is implemented and processing has been done with 90 nm CMOS Technology from TSMC foundry. It is observed that the results obtained, are far better than the FPGA implementation reported earlier in the literature.
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