Redundant Logic Insertion and Latency Reduction in Self‐Timed Adders

Balasubramanian, P.; Edwards, Doug; Toms, William

doi:10.1155/2012/575389

Cited by 14 publications

(18 citation statements)

References 29 publications

(32 reference statements)

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“…Also, two things may be noted with respect to the design of asynchronous arithmetic circuits such as adders: i) strongindication is not usually preferred since it always encounters the worst-case latencies and cycle time [42] [43], requires relatively more area, and dissipates relatively higher average power compared to the rest, and ii) weak-indication and early output adders are preferable, and among these the early output adders are more preferable from the perspectives of latencies, cycle time, area occupancy, and average power dissipation. These two observations have been confirmed in several publications on asynchronous adders with/without redundant logic [44] when targeting accurate and approximate computing by considering diverse architectures such as ripple carry [45 -56], carry lookahead [57 -60], and carry select [61] while employing homogeneous or heterogeneous delay-insensitive data encodings and following 4-phase returnto-zero or 4-phase return-to-one handshaking. However, for the design of datapath components such as multiplexers and demultiplexers, strong-indication may be preferred although it could result in more area, power and delay.…”

Section: Discussionmentioning

confidence: 70%

Comments on “Asynchronous Logic Implementation Based on Factorized DIMS”

Balasubramanian¹

2018

Preprint

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with respect to two main problematic issues: i) the gate orphan problem implicit in the factorized DIMS approach discussed in the referenced article which affects its strong-indication, and ii) how the enumeration of product terms to represent the synthesis cost is skewed in the referenced article because the logic expression contains sum of products and also product of sums. It is observed that the referenced article has not provided a general logic synthesis algorithm excepting only an example illustration involving a 3-input AND logic function. The absence of a general logic synthesis algorithm would make it difficult to reproduce the research described in the referenced article. Moreover, the example illustration in the referenced article describes an unsafe logic decomposition which is not suitable for the multi-level synthesis of strong-indication asynchronous circuits. Further, a logic synthesis method which safely decomposes the DIMS solution to synthesize multi-level strong-indication asynchronous circuits is available in the existing literature, which was neither cited nor taken up for comparison in the referenced article, which is another drawback. Subsequently, it is concluded that the referenced article has not advanced existing knowledge in the field but on the contrary, has caused confusions. Hence, in the interest of readers, this paper additionally highlights some important and relevant literature which provide valuable information about robust asynchronous circuit synthesis techniques which employ delay-insensitive codes for data representation and processing and the 4-phase return-to-zero handshake protocol for data communication.

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Section: Discussionmentioning

confidence: 70%

Comments on “Asynchronous Logic Implementation Based on Factorized DIMS”

Balasubramanian¹

2018

Preprint

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“…The advantage of redundant lookahead carry outputs is that they can enable reductions in the forward latency and the reverse latency, and hence can reduce the cycle time. Redundant logic insertion has been shown to facilitate a reduction in the latency [43] at the expenses of meagre increases in the area and power dissipation compared to their non-redundant counterparts. This work showcases how the redundant carry output logic of an asynchronous BCLARC/hybrid BCLARC-RCA would help to significantly reduce the cycle time and thereby achieve less power-cycle time product (PCTP) compared to an asynchronous BCLA (with no redundant carry output logic).…”

Section: Datapaths Traversed In Asynchronous Addersmentioning

confidence: 99%

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

2018

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Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

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“…However, higher bit-width multiplications should have to be considered to unravel the reality. Nevertheless, both [30] and [31] present full adder designs which incorporate redundant logic, and it was shown in [43] that logic redundancy could help to significantly reduce the latencies and the cycle time at almost no increase in the area or average power dissipation.…”

Section: Conclusion and Scope For Further Workmentioning

confidence: 99%

Indicating Asynchronous Multipliers

Balasubramanian

Maskell

Mastorakis

2018

2018 2nd European Conference on Electrical Engineering and Computer Science (EECS)

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Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of indicating asynchronous multipliers, which are inherently elastic and are robust to timing, process, and parametric variations, and are modular. We consider the physical implementation of many weak-indication asynchronous multipliers using a 32/28-nm CMOS technology by adopting the array multiplier architecture. The multipliers are synthesized in a semi-custom ASIC-design style. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols are considered for the data communication. The multipliers are realized using strong-indication or weak-indication full adders. Strong-indication 2-input AND function is used to generate the partial products in the case of both RTZ and RTO handshaking. The full adders considered are derived from different indicating asynchronous logic design methods. Among the multipliers considered, a weak-indication asynchronous multiplier utilizing the biased weak-indication full adder is found to be efficient in terms of the cycle time and the power-cycle time product with respect to both RTZ and RTO handshaking. Also, the 4-phase RTO handshake protocol is found to be preferable than the 4phase RTZ handshake protocol for achieving enhanced optimizations in the design metrics.

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Redundant Logic Insertion and Latency Reduction in Self‐Timed Adders

Cited by 14 publications

References 29 publications

Comments on “Asynchronous Logic Implementation Based on Factorized DIMS”

Comments on “Asynchronous Logic Implementation Based on Factorized DIMS”

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Indicating Asynchronous Multipliers

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