Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Abstract

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

“…Generally, early output QDI circuits are preferable to strong-and weak-indication circuits as the former can enable better optimizations in the design metrics compared to the latter. This is confirmed by the efficient designs of QDI early output adders, which are reported in the literature [39,40]. After the receipt of some primary inputs, early output circuits can process and produce all the primary outputs.…”

“…Sophisticated timing assumptions may be necessary to overcome gate orphans which may not be practically realizable [38]. Gate and wire orphans have been clearly illustrated through some examples in [32,39,42], and an interested reader may refer to these for the details.…”

“…For RTO handshaking, rising signal transitions will be encountered for the application of the spacer, and falling signal transitions will be encountered for the application of data. The monotonic cover constraint has been described through an example in [39] and an interested reader is referred to the same for the details.…”

Indicating Asynchronous Multipliers

“…(X1, X0) and (Y1, Y0) are the inputs of the 2-input AND function and (Z1, Z0) is its output. A3B3 P1 P2 P3 P4 P5 P6 P7 A0B3 A1B3 A2B3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Traversal of data path for the application of data and spacer in the multiplier array References [1] [23] [41] provide practical examples for the transformation of an asynchronous logic corresponding to the RTZ protocol into that that corresponds to the RTO protocol and vice-versa. The rules for the logical transformation between the RTZ and RTO handshake protocols are given in [25] along with the proofs.…”

“…Addition is a basic arithmetic operation that forms the basis of other important arithmetic operations such as multiplication, division etc. Recently, in [1], different asynchronous implementations of the adder were discussed. This paper considers the robust asynchronous implementations of the multiplier since multiplication is also a common arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications [2].…”