Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter

Kinoshita, Kentaro; Tsunoda, Koji; Sato, Yoshiaki; Noshiro, Hideyuki; Yamazaki, Yoichi; Fukano, T.; Yagaki, S.; Aoki, Masaki; Sugiyama, Yoshihiro

doi:10.1109/nvsmw.2007.4290583

Cited by 19 publications

(9 citation statements)

References 1 publication

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“…By driving the transistor from the linear into the saturation regime, we can limit the current through the memristor, that is, implement current-compliance. The 1T1M write circuitry , is shown in the inset of Figure . A standard 4-probe setup was used to switch the memristor with a NMOS field effect transistor (FET) connected in series.…”

Section: Resultsmentioning

confidence: 99%

Continuous Electrical Tuning of the Chemical Composition of TaO_x-Based Memristors

et al. 2012

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TaO(x)-based memristors have recently demonstrated both subnanosecond resistance switching speeds and very high write/erase switching endurance. Here we show that the physical state variable that enables these properties is the oxygen concentration in a conduction channel, based on the measurement of the thermal coefficient of resistance of different TaO(x) memristor states and a set of reference Ta-O films of known composition. The continuous electrical tunability of the oxygen concentration in the channel, with a resolution of a few percent, was demonstrated by controlling the write currents with a one transistor-one memristor (1T1M) circuit. This study demonstrates that solid-state chemical kinetics is important for the determination of the electrical characteristics of this relatively new class of device.

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Section: Resultsmentioning

confidence: 99%

Continuous Electrical Tuning of the Chemical Composition of TaO_x-Based Memristors

et al. 2012

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“…However, these devices have only been demonstrated to retain stored data up to 8 months at room temperature and also required a high RESET current (;2 mA), independent of the resistance RAM (RRAM) device area. It has been shown [67] that the RESET current can be reduced to approximately 200 lA in the Pt/NiO/Pt system by limiting both the current that flows during the SET transition and the parasitic currents due to stray capacitance.…”

Section: Resistive Ram and Solid-electrolyte Memorymentioning

confidence: 99%

Overview of candidate device technologies for storage-class memory

et al. 2008

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Storage-class memory (SCM) combines the benefits of a solidstate memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitrideoxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

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“…The relationships of I reset versus I comp and R on versus I comp for I comp ≥ 1 mA have been reported based on 1R architecture, in which the compliance current is controlled by connecting an external transistor [1]- [3]. However, the aforementioned two relationships have rarely been reported for I comp < 1 mA in 1T1R-architecture RRAM device based on standard CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

In Situ Observation of Compliance-Current Overshoot and Its Effect on Resistive Switching

Wan

Zhou

et al. 2010

IEEE Electron Device Lett.

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The compliance-current dependence of the resistiveswitching behaviors is investigated in TaN/Cu x O/Cu memory devices with 1R architecture and 1T1R architecture, respectively. The correlation of reset current I reset and ON-state resistance R on can be verified by adjusting the compliance current I comp . Meanwhile, I reset and R on become independent on I comp in the 1R architecture when I comp is below 1 mA. A serious compliance-current overshoot phenomenon is in situ observed in 1R-architecture device, and it remarkably affects the resistive-switching characteristics because the compliance current dominates the memory behaviors. Therefore, resistive-switching investigation based on 1T1R architecture is much more reliable.

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Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter

Cited by 19 publications

References 1 publication

Continuous Electrical Tuning of the Chemical Composition of TaO_x-Based Memristors

Continuous Electrical Tuning of the Chemical Composition of TaO_x-Based Memristors

Overview of candidate device technologies for storage-class memory

In Situ Observation of Compliance-Current Overshoot and Its Effect on Resistive Switching

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Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter

Cited by 19 publications

References 1 publication

Continuous Electrical Tuning of the Chemical Composition of TaOx-Based Memristors

Continuous Electrical Tuning of the Chemical Composition of TaOx-Based Memristors

Overview of candidate device technologies for storage-class memory

In Situ Observation of Compliance-Current Overshoot and Its Effect on Resistive Switching

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Product

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Continuous Electrical Tuning of the Chemical Composition of TaO_x-Based Memristors

Continuous Electrical Tuning of the Chemical Composition of TaO_x-Based Memristors