Reduction of off-state drain leakage in InGaAs-based metal-oxide-semiconductor field-effect transistors

Mo, Jianchu; Lind, Erik; Roll, Guntrade; Wernersson, Lars‐Erik

doi:10.1063/1.4891569

Cited by 15 publications

(7 citation statements)

References 11 publications

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“…As the bandgap in the cap is reduced, the tunneling barrier for BTBT also shrinks and BTBT at the drain edge of the channel is enhanced. This is consistent with experimental observations in [5]. The increase in I BTBT , however, is significantly weaker than the bipolar gain reduction and OFF-state leakage follows the trend of the latter.…”

Section: B Inas Composition In Channel and Capsupporting

confidence: 92%

Physics and Mitigation of Excess OFF-State Current in InGaAs Quantum-Well MOSFETs

Lin

Antoniadis

Alamo

2015

IEEE Trans. Electron Devices

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A number of recent reports have noted excess OFF-state leakage current (I OFF ) in scaled InGaAs quantum-well nMOSFETs. There is growing evidence that a combination of band-to-band tunneling (BTBT) and a floating-body bipolar gain effect is responsible for this. Unless this issue is effectively addressed, the scaling potential of this transistor structure will be compromised. This paper presents a detailed study of the physics of I OFF and explores I OFF reduction strategies through 2-D device simulations that have been calibrated with experiments. In essence, under OFF conditions at even moderate values of V ds , a BTBT process at the drain-end generates holes in the channel and thereby reduces the source-channel potential barrier. This results in injection of electrons into the channel that contribute to enhanced I OFF while the holes are injected into the source where they recombine. In a nanoscale device, the bipolar effect that is at play here can have a very large current gain and amplify many fold even a small BTBT current. A study of approaches to mitigating this effect is analyzed here. It is concluded that the most effective strategy is to minimize the bipolar current gain rather than BTBT in scaled transistors.Index Terms-III-V, band-to-band tunneling (BTBT), bipolar effect, floating body, MOSFETs, quantum-well (QW), self-aligned.

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Section: B Inas Composition In Channel and Capsupporting

confidence: 92%

Physics and Mitigation of Excess OFF-State Current in InGaAs Quantum-Well MOSFETs

Lin

Antoniadis

Alamo

2015

IEEE Trans. Electron Devices

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“…The III-V layers are first recessed by a Cl-based RIE [15], followed by digital etch. The III-V RIE is self-aligned to the SiO 2 hard mask, and stops a few nanometers above the InP barrier.…”

Section: Device Fabricationmentioning

confidence: 99%

“…For example, we have recently identified the band-to-band tunneling amplified by a parasitic bipolar effect as the cause of excess OFF-state leakage current at high drain bias in InGaAs MOSFETs [12], [13]. Mitigating this is an important priority for future scaled InGaAs MOSFETs [7], [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Impact of Intrinsic Channel Scaling on InGaAs Quantum-Well MOSFETs

Lin

Antoniadis

Alamo

2015

IEEE Trans. Electron Devices

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Using a novel gate-last process scheme that affords precise channel thickness control, we have fabricated self-aligned InGaAs quantum-well (QW) MOSFETs. Devices with a channel thickness between 3 and 12 nm, and a gate length between 40 nm and 5 µm are fabricated on a heterostructure that includes a composite InGaAs/InAs QW and an InP barrier. It is observed that channel thickness has a strong impact on the device characteristics. In general, a thick channel is beneficial to ON-state figures of merit, including transconductance and effective carrier mobility. However, a thin channel is beneficial to OFF-state metrics, such as subthreshold swing and drain-induced barrier lowering (DIBL). The InAs composition and effective mass that electrons experience in the channel emerges as a factor that significantly affects channel mobility and presumably the transport characteristics of these devices. The subthreshold swing and DIBL are found to follow a classic scaling behavior. This suggests that the InGaAs QW MOSFETs are at the limit of scaling around L g = 50 nm.Index Terms-III-V, MOSFETs, quantum-well (QW), self-aligned.

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“…However, one of the most critical problems that must be solved to realize III-V MOSFETs is the formation of a stable MOS interface with low trap density [7]. Compared with the SiO 2 /Si system, the III-V native oxides negatively affect fermi-level pinning and current drift [8][9][10]. The atomic layer deposited (ALD) Al 2 O 3 dielectric in surface InGaAs channel MOSFETs can achieve a thermally stable interface and large band offsets, as confirmed by the previous research on the dielectric layer of InGaAs MOSFETs [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Reliability of Buried InGaAs Channel n-MOSFETs With an InP Barrier Layer and Al2O3 Dielectric Under Positive Bias Temperature Instability Stress

Gao

et al. 2020

Front. Phys.

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The positive bias temperature instability (PBTI) reliability of buried InGaAs channel n-MOSFETs with an InP barrier layer and Al 2 O 3 gate dielectric under medium field (2.7 MV/cm) and high field (5.0 MV/cm) are investigated in this paper. The Al 2 O 3 /InP interface of the insertion of an InP barrier layer has fewer interface and border traps compared to that of the Al 2 O 3 /InGaAs interface. The subthreshold slope, transconductance, and shift of V g are studied by using the direct-current I d -V g measurements under the PBTI stress. The experimental results show that the degradation of positive V g under the medium field stress is mainly caused by the acceptor trap, while the donor trap under the high field stress become dominant in the subthreshold region, which leads to the negative shift in V g . The medium field stress-induced acceptor traps are attributed by the InP barrier layer in the subthreshold region, resulting that the low leakage current can be achieved in the buried InGaAs channel n-MOSFETs with an InP barrier layer compared to the surface InGaAs channel n-MOSFETs.

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Reduction of off-state drain leakage in InGaAs-based metal-oxide-semiconductor field-effect transistors

Cited by 15 publications

References 11 publications

Physics and Mitigation of Excess OFF-State Current in InGaAs Quantum-Well MOSFETs

Physics and Mitigation of Excess OFF-State Current in InGaAs Quantum-Well MOSFETs

Impact of Intrinsic Channel Scaling on InGaAs Quantum-Well MOSFETs

Reliability of Buried InGaAs Channel n-MOSFETs With an InP Barrier Layer and Al2O3 Dielectric Under Positive Bias Temperature Instability Stress

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