Reducing test data volume using external/LBIST hybrid test patterns

Das, Dibyendu; Touba, N.A.

doi:10.1109/test.2000.894198

Cited by 90 publications

(25 citation statements)

References 10 publications

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“…Chandra and Chakrabarty have proposed test vector compression techniques based on Golomb codes [3,4] and frequency directed run-length (FDR) codes [5]. Test vector compression based on hybrid BIST techniques have been described in [6] and [15]. In [8], a test vector compression technique based on geometric primitives is proposed.…”

Section: Related Workmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.

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Section: Related Workmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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“…In [5], a hybrid BIST approach was proposed where some of the scan chains in a STUMPS architecture are filled with deterministic test data from the tester while the rest of the scan chains are filled from the pseudorandom pattern generator (PRPG). The set of scan chains receiving deterministic data is rotated in a round-robin fashion.…”

Section: Introductionmentioning

confidence: 99%

Weighted pseudorandom hybrid BIST

Jas

Krishna

Touba

2004

IEEE Trans. VLSI Syst.

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Abstract-This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. No test points or any modifications are made to the function logic. The paper describes the proposed hybrid BIST architecture as well as two different ways of storing the weight sets, which are an integral part of this scheme.

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“…Consequently, mixed mode BISTs have been proposed, combining pseudo-random tests along with testcube information [3,11,12]. Reseeding of LFSRs has also been proposed.…”

Section: Introductionmentioning

confidence: 99%