Weighted pseudorandom hybrid BIST

Abstract

Abstract-This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. No test points or any modifications are made to the function logic. The paper describes the proposed hybrid BIST architecture as well as two different ways of storing the weight sets, which are an integral part of this scheme.

Scan BIST with biased scan test signals

“…[6]. Most recently, new techniques were proposed by Jas, Krishna and Touba [4] to compress and store weight sets, which can reduce tester storage requirements and tester bandwidth requirements by orders of magnitude. However, most biased random testing methods need to store multiple weight sets on-chip, and multiple session testing is usually necessary, which can make the control logic very complex.…”

XWRC: externally-loadedweighted random pattern testing for input test data compression

“…In Table 2, we compare the proposed method with the weighted pseudo-random hybrid BIST method [8]. Since we use a single scan chain in our experiments (note that compression ratio achieved by the proposed method is independent of the number of scan chains), results for [8] are shown for the lowest (8) scan chain versions of benchmark circuits published in that paper.…”

“…Unlike [13] where weight sets are stored in a RAM, in [21,22], weight sets are hardwired into random logic (decoder) to minimize hardware overhead. Recently, an application of weighted random pattern testing techniques to test data compression was presented in [8,11,12], where weight data of the inputs that have signal probability other than 0.5 are stored in an on-chip memory and accessed to generate weighted random patterns during test application. Test data for inputs that have 0.5 signal probability are generated by an on-chip random pattern generator.…”

“…One advantage of using this technique is that the compression achieved by the proposed technique is not bounded by the number of specified bits as is the case with traditional LFSR reseeding techniques. The main difference between [8,11,12] and the proposed method is in the architecture of decompressor.…”

“…[8] proposes generating weights by a PLA in addition to storing weight sets into a RAM. In contrast, the proposed method does not require a RAM/ROM to store weight sets; the weight signals are generated from reseeding LFSRs.…”