An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of low power circuits and bare die that would otherwise require expensive heat removal equipment for testing at high speeds. The proposed ATPG exploits all don't cares that occur during scan shifting, test application, and response capture to minimize switching activity in the circuit under test. Furthermore, an ATPG that maximizes the number of state inputs that are assigned don't care values, has been developed. The proposedtechnique has been implemented and used to generate tests for full scan versions of ISCAS 89 benchmark circuits. These tests decrease the average number of transitions during test by 19% to 89%, when compared with those generated by a simple PODEM implementation.

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The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a response shaper, to reshape the scan-out responses before feeding them to a space compactor. Along with the proposed reshaping algorithm, response shapers can help the space compactor to reduce the number of undetectable modeled and un-modeled faults in the presence of unknown values. Moreover, the proposed compaction scheme is ATPGindependent and its hardware requirement is pattern-independent.In our experiments, we use a simple XOR compactor as the space compactor to evaluate the effectiveness of the response shaper. The results show that the number of undetectable faults and unobservable scan-out responses can be significantly reduced in comparison with the results of a convolutional compactor. The number of the extra scan-in bits required for the control signals of the response shapers is only a small fraction of the total test data volume. Also, its hardware overhead is acceptable and the runtime of the reshaping algorithm is scalable for large industrial designs.

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