Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Lacruz, Jesus O.; García-Herrero, Francisco; Canet, M. J.; Valls, Javier

doi:10.1109/tvlsi.2016.2514484

Cited by 29 publications

(33 citation statements)

References 24 publications

(56 reference statements)

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“…13 except for the fact that the SN includes four more 1B ECNs (i.e., the HB(10, 4, 2) CN architecture). The T-MM performance of a code of same length and coding rate provided in [8] is also presented in Fig. 15.…”

Section: A Performancementioning

confidence: 99%

“…However, the performance gap may come from the use of different parity check matrices. In [8] the authors consider a d c = 24, d v = 3 code with an array dispersion construction while we use a d c = 16, d v = 2 code constructed using optimized coefficients for the parity checks [25].…”

Section: A Performancementioning

confidence: 99%

“…For a fair comparison with the T-MM architecture [8] [9], the full decoder is considered since the T-MM-base decoder uses a different VN architecture. We implemented a complete decoder architecture based on an HB(10,4,2) CN over GF(64) which is connected to 16 VNs.…”

Section: Comparison With the T-mm Architecturementioning

confidence: 99%

“…The synthesis results are given in Table VI. We considered the same clock frequency as [8] F clk = 350 MHz to compute the HB efficiency and throughput for a fair comparison. Those results triggers us few comments, first, this comparison is not really fair for T-MM since a higher variable and check node degree is used for T-MM (d v = 3, d c = 24) compared with HB architecture (d v = 2, d c = 16).…”

Section: Comparison With the T-mm Architecturementioning

confidence: 99%

“…The Trellis-EMS (T-EMS) introduced in [6] avoids the long latency of the FB computation but its hardware complexity highly increases with q when a parallel implementation is considered. The complexity of the T-EMS was reduced with the one-minimum T-EMS [7] and the Trellis Min-Max (T-MM) [8] [9] algorithms.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid Check Node Architectures for NB-LDPC Decoders

Marchand

Boutillon

Harb

et al. 2019

IEEE Trans. Circuits Syst. I

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This paper proposes a unified framework to describe check node architectures of Non-Binary LDPC decoders. Forward-Backward, Syndrome-Based and Pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This work is specially impacting check nodes of high degrees (or high coding rates). Results of 28 nm ASIC post-synthesis for a check node of degree 12 (i.e. code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed Hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared to the classical Forward-Backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256) and these preliminary results open the road to high decoding throughput, high rate, and high order Galois Field NB-LDPC decoder with reasonable hardware complexity.

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Section: A Performancementioning

confidence: 99%

Section: A Performancementioning

confidence: 99%

Section: Comparison With the T-mm Architecturementioning

confidence: 99%

Section: Comparison With the T-mm Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hybrid Check Node Architectures for NB-LDPC Decoders

Marchand

Boutillon

Harb

et al. 2019

IEEE Trans. Circuits Syst. I

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Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Harb

Ghouwayel

Conde-Canencia

et al. 2022

J Sign Process Syst

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This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of $$10^{-3}$$ 10 - 3 .

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