Abstract-This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended MinSum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design.
This paper proposes a unified framework to describe check node architectures of Non-Binary LDPC decoders. Forward-Backward, Syndrome-Based and Pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This work is specially impacting check nodes of high degrees (or high coding rates). Results of 28 nm ASIC post-synthesis for a check node of degree 12 (i.e. code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed Hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared to the classical Forward-Backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256) and these preliminary results open the road to high decoding throughput, high rate, and high order Galois Field NB-LDPC decoder with reasonable hardware complexity.
Wireless terabit-per-second (Tb/s) links will become an urgent requirement within the next 10 years. However, current methodology for high data rate wireless communication that keep increasing the M-ary modulation schemes and the order of MIMO spatial multiplexing cannot reach Tb/s with a low power consumption. Thus, a new methodology is required with a large bandwidth in the millimeter-wave (mm-Wave) and sub-Terahertz (sub-THz) bands above 90GHz. In addition, it must be able to provide an extremely high spectral efficiency with a low energy consumption. Note that this consumption can be reduced by using constant-envelope modulations such as continuous phase modulation (CPM). However, the CPM has a very low spectral efficiency that limits the desired data rate. This paper suggests a new methodology to reach 1 Tb/s with a low power consumption by using power efficient single carrier with Index Modulation (IM). Simulation results under various uncorrelated/correlated fading channels show that the systems with power efficient modulations as CPM or QPSK can achieve Tb/s with a good performance. Moreover, the link budget and power estimation prove that the constant and near-constant envelope modulations require less than 1−3 Watts for 1 Tb/s with 10 −4 un-coded BER. Finally, this paper shows that conveying most of the information bits using IM to reach an ultra-high data rate is more power efficient than high order MIMO spatial multiplexing with large M-ary QAM as used in LTE.
A novel domain for Index Modulation (IM) named "Filter Domain" is proposed. This new domain generalizes many existing modulations and IM domains. In addition, a novel scheme "Filter Shape Index Modulation" (FSIM) is proposed. This FSIM scheme allows a higher Spectral Efficiency ( SE) gain than the time and frequency IM dimensions in Single-Input Single-Output (SISO) systems. In the FSIM system, the bitstream is mapped using an Amplitude Phase Modulation (APM) as QAM or PSK, and an index of a filter-shape c hanging a t the symbol rate. This filter s hape, b eing c hanged a t e ach symbol, enables a SE gain in SISO system without sacrificing a ny time or frequency resources. Compared to an equivalent 8QAM and 16QAM schemes and at the same SE, the FSIM with QPSK using 2 and 4 non-optimal filter s hapes a chieves a g ain o f 3.8 dB and 1.7 dB respectively at BER= 10 −4 , and this superiority is maintained in frequency selective fading channel compared to equivalent SISO-IM schemes. A low complexity detection scheme, approaching the maximum likelihood detector performance, is proposed along with a full performance characterization in terms of theoretical probability of filter i ndex e rror a nd B ER lower bound. Finally, FSIM can achieve better spectral and energy efficiencies w hen a fi lter ba nk an d an IS I ca ncellation technique are optimally designed.
This paper presents an efficient architecture design for Elementary Check Node processing in Non-Binary Low-Density Parity-Check decoders based on the Extended Min-Sum algorithm. This architecture relies on a simplified version of the Bubble Check algorithm and is implemented by the means of FIFOs. The adoption of this new design at the Check Node level results in a high-rate low-cost full-pipelined processor. A proof-of-concept implementation of this processor shows that the proposed architecture halves the occupied FPGA surface and doubles the maximum frequency without modifying the input/output behavior of the previous one.
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