This paper proposes a unified framework to describe check node architectures of Non-Binary LDPC decoders. Forward-Backward, Syndrome-Based and Pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This work is specially impacting check nodes of high degrees (or high coding rates). Results of 28 nm ASIC post-synthesis for a check node of degree 12 (i.e. code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed Hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared to the classical Forward-Backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256) and these preliminary results open the road to high decoding throughput, high rate, and high order Galois Field NB-LDPC decoder with reasonable hardware complexity.
This paper deals with reduced-complexity NB-LDPC check node implementation based on the Extended Min-Sum algorithm. We propose to apply a recently introduced presorting technique to the forward-backward architecture. The presorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees).
In this paper, we present a Barrel-Shifter of size n extended by an additional layer that can handle any circular permutation on a vector of size m, m ≤ n, thanks to a specific initial positioning of the data. The construction of the so-called Extended Barrel-Shifter is motivated by the hardware decoder constraint related to the Low-Density Parity-Check (LDPC) code recently adopted for the 5G mobile standard. The proposed algorithm requires 42 % less multiplexers than the best stateof-the-art solution for n = 384 of the 5G LDPC standard. This proposal is also able to process several inputs in parallel without extra hardware cost.
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