Pre-Sorted Forward-Backward NB-LDPC Check Node Architecture

Abstract

This paper deals with reduced-complexity NB-LDPC check node implementation based on the Extended Min-Sum algorithm. We propose to apply a recently introduced presorting technique to the forward-backward architecture. The presorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees).

Hybrid Check Node Architectures for NB-LDPC Decoders

“…5) and the RE units implementation are also provided. The sorter is implemented using a serial architecture as in [14], and the switch is a cross bar switch. The minimum clock period (P clk ) is given in nanoseconds with a clock uncertainty of 0.05 ns and a setup time of 0.02 ns.…”

“…As proposed in [14], the notion of potential bubbles is proposed by specifying the index variation ranges n a and n b of the two entries A and B, i.e. 0 ≤ a < n a and 0 ≤ b < n b and the one of the output C as n c , i.e.…”

“…Step 3 (decorrelation and RE): and unreliable inputs. This polarization of the inputs makes some deviation paths (for the SB CN [13]) or some potential bubbles (for the FB CN [14]) very unlikely to contribute to an output. The suppression of those useless configurations leads to significant hardware saving without affecting performance.…”

“…For this, we perform a statistical study based on Monte-Carlo simulation that traces the paths of the GF symbols that contribute to the output of the CN, in their way across the different ECNs. This statistical study [14] identifies in each ECN how often a given bubble contributes to an output. This information allows pruning the bubbles that never or rarely contribute.…”

“…for high d c values. Recently, we showed that sorting the input vector of the CN according to a reliability criteria [13] [14] allows significant reduction of the hardware complexity of the CN architecture without affecting performance. This technique, called "presorting", has been successfully combined with the SB CN, leading to the PreSorted-SB CN (or PS-SB CN) algorithm [13] and with the FB CN, leading to the PS-FB CN [14].…”